lan9420 Standard Microsystems Corp., lan9420 Datasheet - Page 112

• Manufacturer Part Number: lan9420
• Description: Lan9420/lan9420i Single-chip Ethernet Controller With Hp Auto-mdix Support And Pci Interface
• Manufacturer: Standard Microsystems Corp.

Revision 1.1 (03-31-08)
15:14
BITS
12:3
13
2
Threshold Control Bits (TR)
This field controls the transmit threshold values used by the MIL. This field
is used by the MIL, not the DMAC. This field is used when the SF bit
(DMAC_CONTROL[21]) is cleared.
The intent is to allow the MIL to transfer data to the final destination only
after the threshold value is met.
In 10Mbps mode (TTM = 1) The threshold is set by
DMAC_CONTROL[15:14] as follows:
In 100Mbps mode (TTM = 0) The threshold is set by
DMAC_CONTROL[15:14] as follows:
Start/Stop Transmission Command (ST)
When set, the transmission process is placed in the Running state, and the
DMAC checks the transmit list at the current position for a frame to be
transmitted.
Descriptor acquisition is attempted either from the current position in the list,
which is the transmit list base address set by TX_BASE_ADDR, or from the
position retained when the transmit process was previously stopped. If no
descriptor can be acquired, the transmit process enters the Suspended
state. If the current descriptor is not owned by the DMA Controller, the
transmission process enters the Suspended state and the Transmit Buffer
Unavailable (DMAC_STATUS bit [2]) is set. The Start Transmission
command is effective only when the transmission process is stopped. If the
command is issued before setting the TX_BASE_ADDR, then the DMA
Controller’s behavior will be undefined.
When reset, the transmission process is placed in the Stopped state after
completing the transmission of the current frame. The next descriptor
position in the transmit list is saved, and becomes the current position when
transmission is restarted.
The Stop Transmission command is effective only when the transmission
process is in either Running or Suspended state.
RESERVED
Operate on Second Frame (OSF)
When set, this bit instructs the DMA Controller to process a second frame
of transmit data even before status for the first frame is obtained. This bit
affects the DMA Controller but not the MIL.
--------------------------------------------------------
--------------------------------------------------------
Bit 15
Bit 15
0
0
1
1
0
0
1
1
Bit 14
Bit 14
0
1
0
1
0
1
0
1
Threshold (DWORDS)
Threshold (DWORDS)
DESCRIPTION
012h
018h
020h
028h
020h
040h
080h
100h
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
DATASHEET
112
TYPE
SMSC LAN9420/LAN9420i
R/W
R/W
R/W
RO
DEFAULT
00b
Datasheet
0b
0b
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