mc68hc05pv8a Freescale Semiconductor, Inc, mc68hc05pv8a Datasheet - Page 100
mc68hc05pv8a
Manufacturer Part Number
mc68hc05pv8a
Description
Mc68hc05pv8a Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MC68HC05PV8A.pdf
(196 pages)
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Technical Data
7.5 Port B
7.5.1 Port B Timer Channels and XOR Function
Technical Data
FROM PC0 OR C4
PB0
PC2
PB2
Figure 7-6 Mapping Ports to Timer Capture Channels
Port B is a 5-bit bidirectional port, shared with timer and PWM channels
(TCAP, TCMP, PWM). An XOR function is provided for one timer
capture channel.
The port B data register is at $0001 and the data direction register (DDR)
is at $0005. Reset does not affect the data registers, but clears the data
direction registers, thereby returning the ports to inputs. Writing a one to
a DDR bit sets the corresponding port bit to output mode.
The port pins PB0–PB3 are shared with the 16-bit timer channels
(TCAP1–2, TCMP1–2). The timer capture channel TCAP1 can be driven
by the XOR of two channels if TXOR bit in the I/O Configuration Register
is set (see
bit 5 of the Port B Data Register.
Freescale Semiconductor, Inc.
For More Information On This Product,
0
1
0
1
Figure
PB0IC
PB2IC
Go to: www.freescale.com
Input/Output Ports
7-6).TCAP1 status can be read by the CPU by polling
0
1
TXOR
TCAP1
MC68HC(8)05PV8/A — Rev. 1.9
Channel 1
Channel 2
Capture
Capture
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