mc68hc908lj24 Freescale Semiconductor, Inc, mc68hc908lj24 Datasheet - Page 237
mc68hc908lj24
Manufacturer Part Number
mc68hc908lj24
Description
M68hc08 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MC68HC908LJ24.pdf
(464 pages)
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12.10.5 RTC Status Register (RTCSR)
MC68HC908LJ24/LK24 — Rev. 2.1
Freescale Semiconductor
Address:
The RTC status register contains eight status flags. When a flag is set
and the corresponding interrupt enable bit is also set, a CPU interrupt
request is generated.
ALMF — Alarm Flag
CHRF — Chronograph Flag
Reset:
Read:
Write:
This clearable, read-only bit is set when the value in the RTC hour and
minute counters matches the value in the alarm hour and alarm
minute registers. When the ALMIE bit in RTCCR1 is set, ALMF
generates a CPU interrupt request. In normal operation, clear the
ALMF bit by reading RTCSR with ALMF set and then reading the
alarm hour register (ALHR). Reset clears ALMF.
This clearable, read-only bit is set on every tick of the chronograph
counter (every counter count). The tick is on every 1/128 seconds
(see
RTCCR1 is set, CHRF generates a CPU interrupt request. In normal
operation, clear the CHRF bit by reading RTCSR with CHRF set and
then reading the chronograph data register (CHRR). Reset clears
CHRF.
1 = RTC hour and minute counters matches the
0 = No matching between hour and minute counters and alarm
1 = A chronograph counter tick has occurred
0 = No chronograph counter tick has occurred
12.5.4 Chronograph
$0044
ALMF
alarm hour and minute registers
hour and minute registers
0
Figure 12-10. RTC Status Register (RTCSR)
Real Time Clock (RTC)
= Unimplemented
CHRF
0
DAYF
0
Functions). When the CHRIE bit in
HRF
0
MINF
0
SECF
0
Real Time Clock (RTC)
TB1F
0
RTC Registers
Data Sheet
TB2F
0
237
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