mc68hc908lj24 Freescale Semiconductor, Inc, mc68hc908lj24 Datasheet - Page 159
mc68hc908lj24
Manufacturer Part Number
mc68hc908lj24
Description
M68hc08 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MC68HC908LJ24.pdf
(464 pages)
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9.8 SIM Registers
MC68HC908LJ24/LK24 — Rev. 2.1
Freescale Semiconductor
INT/BREAK
ICLK
IAB
NOTE:
Figure 9-19. Stop Mode Recovery from Interrupt or Break
A break interrupt during stop mode sets the SIM break stop/wait bit
(SBSW) in the SIM break status register (SBSR).
The SIM counter is held in reset from the execution of the STOP
instruction until the beginning of stop recovery. It is then used to time the
recovery period.
To minimize stop current, all pins configured as inputs should be driven
to a logic 1 or logic 0.
The SIM has three memory-mapped registers:
•
•
•
CPUSTOP
NOTE: Previous data can be operand data or the STOP opcode, depending on the last
STOP +1
SIM Break Status Register (SBSR) — $FE00
SIM Reset Status Register (SRSR) — $FE01
SIM Break Flag Control Register (SBFCR) — $FE03
R/W
IDB
IAB
instruction.
System Integration Module (SIM)
STOP ADDR
Figure 9-18. Stop Mode Entry Timing
Figure 9-18
STOP + 2
PREVIOUS DATA
STOP RECOVERY PERIOD
STOP + 2
STOP ADDR + 1
shows stop mode entry timing.
NEXT OPCODE
SP
System Integration Module (SIM)
SP – 1
SAME
SAME
SP – 2
SAME
SIM Registers
SP – 3
Data Sheet
SAME
159
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