adsp2185 Analog Devices, Inc., adsp2185 Datasheet
adsp2185
Available stocks
Related parts for adsp2185
adsp2185 Summary of contents
Page 1
... Hardware and Automatic Data Buffering Automatic Booting of On-Chip Program Memory from Byte-Wide External Memory, e.g., EPROM, or Through Internal DMA Port *ICE-Port is a trademark of Analog Devices, Inc. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use ...
Page 2
... EZ-ICE adapters needed. Due to the small footprint of the EZ-ICE connector, emulation can be supported in final board designs. *All trademarks are the property of their respective holders. *EZ-ICE and SoundPORT are registered trademarks of Analog Devices, Inc. The EZ-ICE • In-target operation • breakpoints • ...
Page 3
The internal result (R) bus connects the computational units so the output of any unit may be the input of any unit on the next cycle. A powerful program sequencer and two dedicated data address generators ensure efficient delivery of ...
Page 4
ADSP-2185 Common-Mode Pins # Input/ Pin of Out- Name(s) Pins put Function RESET 1 I Processor Reset Input Bus Request Input Bus Grant Output BGH 1 O Bus Grant Hung Output DMS 1 O ...
Page 5
RESET is deasserted, the driver should three-state, thus allow- ing full use of the PF2 pin as either an input or output. To minimize power consumption during power-down, configure the programmable flag as an output when connected to a three- ...
Page 6
ADSP-2185 Idle When the ADSP-2185 is in the Idle Mode, the processor waits indefinitely in a low power state until an interrupt occurs. When an unmasked interrupt occurs serviced; execution then continues with the instruction following the IDLE ...
Page 7
The ADSP-2185 uses an input clock with a frequency equal to half the instruction rate; a 16.67 MHz input clock yields processor cycle (which is equivalent to 33 MHz). Normally, instructions are executed in a single processor ...
Page 8
ADSP-2185 Table II. PMOVLAY Memory A13 0 Internal Not Applicable Not Applicable 1 External 0 Overlay 1 2 External 1 Overlay 2 This organization provides for two external 8K overlay segments using only the normal 14 address bits. This allows ...
Page 9
All enable bits, except the BMS bit, default reset, Byte Memory The byte memory space is a bidirectional, 8-bit-wide, external memory space used to store programs and data. Byte memory is accessed using ...
Page 10
ADSP-2185 Table VI. Boot Summary Table MODE C MODE B MODE A Booting Method BDMA feature is used to load the first 32 program memory words from the byte memory space. Program execution is held off until ...
Page 11
BIASED ROUNDING A mode is available on the ADSP-2185 to allow biased round- ing in addition to the normal unbiased rounding. When the BIASRND bit is set to 0, the normal unbiased rounding opera- tions occur. When the BIASRND bit ...
Page 12
ADSP-2185 ® Target Board Connector for EZ-ICE ® The EZ-ICE * connector (a standard pin strip header) is shown in Figure 7. You must add this connector to your target board design if you intend to use the EZ-ICE enough ...
Page 13
RECOMMENDED OPERATING CONDITIONS Parameter Min V 4 AMB ELECTRICAL CHARACTERISTICS Parameter V Hi-Level Input Voltage IH V Hi-Level CLKIN Voltage IH V Lo-Level Input Voltage IL V Hi-Level Output Voltage OH V Lo-Level Output Voltage OL I ...
Page 14
ADSP-2185 ABSOLUTE MAXIMUM RATINGS* Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . –0 Input Voltage . . ...
Page 15
ENVIRONMENTAL CONDITIONS Ambient Temperature Rating – ( AMB CASE Case Temperature in C CASE PD = Power Dissipation Thermal Resistance (Case-to-Ambient Thermal Resistance (Junction-to-Ambient Thermal ...
Page 16
ADSP-2185 CAPACITIVE LOADING Figures 9 and 10 show the capacitive loading characteristics of the ADSP-2185 + 4. 100 150 50 C – Figure 9. ...
Page 17
TIMING PARAMETERS Parameter Clock Signals and Reset Timing Requirements: t CLKIN Period CKI t CLKIN Width Low CKIL t CLKIN Width High CKIH Switching Characteristics: t CLKOUT Width Low CKL t CLKOUT Width High CKH t CLKIN High to CLKOUT ...
Page 18
ADSP-2185 Parameter Interrupts and Flag Timing Requirements: t IRQx, FI, or PFx Setup before CLKOUT Low IFS t IRQx, FI, or PFx Hold after CLKOUT High IFH Switching Characteristics: t Flag Output Hold after CLKOUT Low FOH t Flag Output ...
Page 19
Parameter Bus Request/Grant Timing Requirements Hold after CLKOUT High Setup before CLKOUT Low BS Switching Characteristics: t CLKOUT High to xMS, RD, WR Disable SD t xMS, RD, WR Disable to BG Low SDB t ...
Page 20
ADSP-2185 Parameter Memory Read Timing Requirements Low to Data Valid RDD t A0-A13, xMS to Data Valid AA t Data Hold from RD High RDH Switching Characteristics Pulse Width RP t CLKOUT High to RD Low ...
Page 21
Parameter Memory Write Switching Characteristics: t Data Setup before WR High DW t Data Hold after WR High Pulse Width WP WR Low to Data Enabled t WDE t A0–A13, xMS Setup before WR Low ASW t ...
Page 22
ADSP-2185 Parameter Serial Ports Timing Requirements: t SCLK Period SCK t DR/TFS/RFS Setup before SCLK Low SCS t DR/TFS/RFS Hold after SCLK Low SCH t SCLK Width SCP IN Switching Characteristics: t CLKOUT High to SCLK CC t SCLK High ...
Page 23
Parameter IDMA Address Latch Timing Requirements: t Duration of Address Latch IALP t IAD15–0 Address Setup before Address Latch End IASU t IAD15–0 Address Hold after Address Latch End IAH IACK Low before Start of Address Latch t IKA t ...
Page 24
ADSP-2185 Parameter IDMA Write, Short Write Cycle Timing Requirements: t IACK Low before Start of Write IKW Duration of Write IWP t IAD15–0 Data Setup before End of Write IDSU t IAD15–0 Data Hold after End of ...
Page 25
Parameter IDMA Write, Long Write Cycle Timing Requirements: t IACK Low before Start of Write IKW t IAD15–0 Data Setup before IACK Low IKSU t IAD15–0 Data Hold after IACK Low IKH Switching Characteristics: t Start of Write to IACK ...
Page 26
ADSP-2185 Parameter IDMA Read, Long Read Cycle Timing Requirements: t IACK Low before Start of Read IKR 1 t Duration of Read IRP Switching Characteristics: t IACK High after Start of Read IKHR t IAD15–0 Data Setup before IACK Low ...
Page 27
Parameter IDMA Read, Short Read Cycle Timing Requirements: t IACK Low before Start of Read IKR t Duration of Read IRP Switching Characteristics: t IACK High after Start of Read IKHR t IAD15–0 Data Hold after End of Read IKDH ...
Page 28
ADSP-2185 A4/IAD3 1 PIN 1 2 A5/IAD4 IDENTIFIER GND 3 4 A6/IAD5 A7/IAD6 5 6 A8/IAD7 A9/IAD8 7 8 A10/IAD9 A11/IAD10 9 10 A12/IAD11 A13/IAD12 11 12 GND CLKIN 13 14 XTAL 15 VDD 16 CLKOUT 17 GND 18 VDD ...
Page 29
The ADSP-2185 package pinout is shown in the table below. Pin names in bold text replace the plain text named functions when Mode sign separates two functions when either function can be active for either ...
Page 30
ADSP-2185 Ambient Temperature Part Number Range ADSP-2185KST-115 +70 C ADSP-2185BST-115 – +85 C ADSP-2185KST-133 +70 C ADSP-2185BST-133 – +85 C *ST = Plastic Thin Quad Flatpack (TQFP). 100-Lead Metric Thin ...
Page 31
–31– ...
Page 32
–32– ...