adsp-21267skstz Analog Devices, Inc., adsp-21267skstz Datasheet - Page 26

• Manufacturer Part Number: adsp-21267skstz
• Description: Sharc Processor
• Manufacturer: Analog Devices, Inc.

ADSP-21267
Memory Write—Parallel Port
Use these specifications for asynchronous interfacing to memo-
ries (and memory-mapped peripherals) when the
ADSP-21267 is accessing external memory space.
Table 20. 8-bit Memory Write Cycle
1
Parameter
Switching Characteristics:
t
t
t
t
t
t
t
t
t
t
t
D = (Data Cycle Duration) x t
H = t
On reset, ALE is an active high cycle. However, it can be reconfigured by software to be active low.
ALEW
ALERW
ADAS
ADAH
WW
ADWL
ADWH
ALEHZ
DWS
DWH
DAWH
CCLK
(if a hold cycle is specified, else H = 0)
AD[15:8
AD[7:0]
ALE Pulse Width
ALE Deasserted to Read/Write Asserted
Address/Data [15:0] Setup Before ALE Deasserted
Address/data [15:0] Hold After ALE Deasserted
WR Pulse Width
Address/Data [15:8] to WR Low
Address/Data [15:8] hold after WR High
ALE Deasserted
Address/Data [7:0] Setup Before WR High
Address/Data [7:0] Hold After WR High
Address/Data to WR High
ALE
WR
RD
]
CCLK
PRELIMINARY TECHNICAL DATA
1
VALID ADDRESS
VALID ADDRESS
to Address/Data[15:0] In High Z
t
ADAS
t
ALEW
Figure 19. Write Cycle For 8-bit Memory Timing
Rev. PrA | Page 26 of 44 | January 2004
t
ADAH
t
ALEHZ
t
ALERW
1
1
t
ADWL
VALID ADDRESS
t
DAWH
t
Min
2 x t
1 x t
2.5 x t
0.5 x t
D - 2
0.5 x t
0.5 x t
0.5 x t
D
0.5 x t
D
WW
VALID DATA
t
DWS
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
– 2
– 1
– 2.0
– 0.8
– 1.5
– 1 + H
– 0.8
– 1.5 + H
t
DWH
t
ADWH
Max
0.5t
CCLK
+ 3.0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns