adsp-21267skstz Analog Devices, Inc., adsp-21267skstz Datasheet - Page 25
adsp-21267skstz
Manufacturer Part Number
adsp-21267skstz
Description
Sharc Processor
Manufacturer
Analog Devices, Inc.
Datasheet
1.ADSP-21267SKSTZ.pdf
(44 pages)
- Current page: 25 of 44
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Table 19. 16-bit Memory Read Cycle
1
Parameter
Timing Requirements
t
t
Switching Characteristics
t
t
t
t
t
t
D = (Data Cycle Duration) x t
H = t
On reset, ALE is an active high cycle. However, it can be reconfigured by software to be active low.
DRS
DRH
ALEW
ALERW
ADAS
ADAH
ALEHZ
RW
CCLK
(if a hold cycle is specified, else H = 0)
Address/Data [15:0] Setup Before RD high
Address/Data [15:0] Hold After RD high
ALE Pulse Width
ALE Deasserted to Read/Write Asserted
Address/Data [15:0] Setup Before ALE Deasserted
Address/Data [15:0] Hold After ALE Deaserted
ALE Deasserted
RD Pulse Width
AD[15:0]
ALE
CCLK
WR
RD
PRELIMINARY TECHNICAL DATA
1
to Address/Data[15:0] In High Z
VALID ADDRESS
Figure 18. Read Cycle For 16-bit Memory Timing
t
ADAS
t
ALEW
Rev. PrA | Page 25 of 44 | January 2004
t
ADAH
t
t
ALERW
ALEHZ
1
1
t
VALID DATA
RW
t
DRS
Min
3.3
0
2 x t
1 x t
2.5 x t
0.5 x t
0.5 x t
D – 2
CCLK
CCLK
CCLK
CCLK
CCLK
t
DRH
– 2
– 1
– 2.0
– 0.8
– 0.8
Max
0.5t
CCLK
ADSP-21267
+ 3.0
ns
Unit
ns
ns
ns
ns
ns
ns
ns
ns
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