lm12458mel-883 National Semiconductor Corporation, lm12458mel-883 Datasheet - Page 31

• Manufacturer Part Number: lm12458mel-883
• Description: 12-bit Sign Data Acquisition System With Self-calibration
• Manufacturer: National Semiconductor Corporation

5.0 Sequencer
Leaving this bit reset to “0” allows the Sequencer to execute
“unprogrammed” instructions, the results of which may be
unpredictable.
The Sequencer’s Instruction Pointer value is readable at any
time and is found in the Status register at Bits 8–10. The
Sequencer can go through eight states during instruction
execution:
the Instruction RAM “00”. This state is one clock cycle long.
This is the “rest” state whenever the Sequencer is stopped
using the reset, a Pause command, or the Start bit is reset
low (“0”). When the Start bit is set to a “1”, this state is one
clock cycle long.
figuration register is set to a “1”, state 2 is 76 clock cycles
long. If the Configuration register’s bit 3 is set to a “1”, state
2 is 4944 clock cycles long.
clock cycles for this state varies according to the value
stored in the Timer register. The number of clock cycles is
found by using the expression below
State 0: The current instruction’s first 16 bits are read from
State 1: Checks the state of the Calibration and Start bits.
State 2: Perform calibration. If bit 2 or bit 6 of the Con-
State 3: Run the internal 16-bit Timer. The number of
(Continued)
31
where 0 ≤ T ≤ 2
value if needed. The number of clock cycles for 12-bit + sign
mode varies according to
where D is the user-programmable 4-bit value stored in bits
12–15 of Instruction RAM “00” and is limited to 0 ≤ D ≤ 15.
The number of clock cycles for 8-bit + sign or “watchdog”
mode varies according to
where D is the user-programmable 4-bit value stored in bits
12–15 of Instruction RAM “00” and is limited to 0 ≤ D ≤ 15.
cycles long.
state takes 44 clock cycles when using the 12-bit + sign
mode or 21 clock cycles when using the 8-bit + sign mode.
The “watchdog” mode takes 5 clock cycles.
State 7: Run the acquisition delay and read Limit #1’s
State 6: Perform first comparison. This state is 5 clock
State 4: Read Limit #2. This state is 1 clock cycle long.
State 5: Perform a conversion or second comparison. This
16
−1.
32T + 2
9 + 2D
2 + 2D
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