cs5317 Cirrus Logic, Inc., cs5317 Datasheet - Page 8

• Manufacturer Part Number: cs5317
• Description: 16-bit, 20 Khz Oversampling A/d Converter
• Manufacturer: Cirrus Logic, Inc.

* t
The second PLL mode is termed Clock Genera-
tion 2 (CLKG2) which generates its 5.12 MHz
clock from a 10 kHz external sampling signal.
Again, output samples are available at the system
sampling rate set by CLKIN, typically 10 kHz.
For the full-rated 10 kHz clock CLKG2 still sets
the filter’s 3 dB point at 5 kHz. Therefore,
CLKG2 provides no oversampling beyond the
Nyquist
(10 kHz : 5 kHz) and its internal digital filter pro-
vides little anti-aliasing value. The CLKG2 mode
is initiated by grounding the MODE pin.
The CS5317 features a third operating mode
called Clock Override (CLKOR). Initiated by ty-
ing the MODE pin to -5V, CLKOR allows the
5.12 MHz master clock to be driven directly into
the CLKIN pin. The CS5317 then processes sam-
ples updating its output register at f
Since all clocking is generated internally, the
CLKOR mode includes a Reset capability which
allows the output samples of multiple CS5317’s
to be synchronized.
The CS5317 also has a CS5316 compatible
mode, selected by tying RST low, and using
MODE (pin 7) as the FSYNC pin. See the
CS5316 data sheet for detailed timing informa-
tion.
8
Clock
Gen. 2
Clock
Gen. 1
Clock
Override
CS5316
dcD
Mode
- Delay from CLKIN rising to DOUT falling = 1 CLKOUT cycle
requirement
CS5316 FSYNC
Symbol
CLKOR
CLKOR
CLKOR
CLKG2
CLKG2
CLKG2
CLKG1
CLKG1
CLKG1
Mode
+5V
Pin
-5V
0V
at
the
RESET
SYNC
HIGH
HIGH
LOW
system
System-level 2X
Table 1. Mode Comparisons
Rate Provides
Oversampling
clkin
Output Word
/256.
level
YES
YES
YES
NO
Analog Design Considerations
DC Characteristics
The CS5317 was designed for signal processing.
Its analog modulator uses CMOS amplifiers re-
sulting in offset and gain errors which drift over
temperature. If the CS5317 is being considered
for low-frequency (< 10 Hz) measurement appli-
cations, Crystal Semiconductor recommends the
CS5501, a low-cost, d.c. accurate, delta-sigma
ADC featuring excellent 60 Hz rejection and a
system-level calibration capability.
The Analog Input Range and Coding Format
The input range of the CS5317 is nominally
with
this gain error, analog input levels should be kept
below
pears MSB-first in 2’s complement format.
Antialiasing Considerations
In applying the CS5317, aliasing occurs during
both the initial sampling of the analog input at f
(~2.5 MHz) and during the digital decimation
process to the 16-bit output sample rate, f
5120.0 (max)
5120.0 (max)
10.0 (max)
20.0 (max)
CLKIN
3686.4
4915.2
(kHz)
14.4
19.2
7.2
9.6
250 mV possible gain error. Because of
2.75V. The converter’s serial output ap-
CLKOUT
1.8432
2.4576
1.8432
2.4576
1.8432
2.4576
(MHz)
2.56
2.56
2.56
2.56
f
sin
DOUT
(kHz)
f
10.0
14.4
19.2
20.0
14.4
19.2
20.0
20.0
sout
7.2
9.6
(kHz)
14.4
19.2
20.0
14.4
19.2
20.0
14.4
19.2
20.0
20.0
F
CS5317
s
out
DS27F4
542.5
406.9
390.6
542.5
406.9
390.6
t
(ns)
N/A
N/A
N/A
N/A
dcD
.
3V,
*
s
in