cs5317 Cirrus Logic, Inc., cs5317 Datasheet - Page 7

• Manufacturer Part Number: cs5317
• Description: 16-bit, 20 Khz Oversampling A/d Converter
• Manufacturer: Cirrus Logic, Inc.

SYSTEM DESIGN WITH THE CS5317
Like a tracking ADC, the CS5317 continuously
samples and converts, always tracking the analog
input signal and updating its output register at a
20 kHz rate. The device can be read at any rate to
create any system-level sampling rate desired up
to 20kHz.
Clocking
Oversampling is a critical function in delta-sigma
A/D conversion. Although system-level output
sample rates typically remain between 7kHz and
20kHz in voiceband applications, the CS5317 ac-
tually samples and converts the analog input at
rates up to 2.56 MHz. This internal sampling rate
is typically set by a master clock which is on the
order of several megahertz. See Table1 for a com-
plete description of the clock relationships in the
various CS5317 operating modes.
DS27F4
Analog
Source
Signal
Analog
Supply
Analog
Supply
VA+
+5V
-5V
Figure 1. System Connection Diagram with Example PLL Components
25 nF
10
10
Conditioning
F
Signal
F
0.1
0.1
25 k
F 0.1
F
18
17
F
12
11
15
AIN
± 2.75V
VCOIN
PHDT
AGND
REFBUF
VA+
VA-
1
14
CS5317
10
10
CLKOUT
MODE
CLKIN
DGND
VD+
DOUT
DATA
DOE
VD-
RST
2
10
Some systems such as echo-canceling modems,
though, require the output sampling rate to be
locked to a sampling signal which is 20 kHz or
below. For this reason the CS5317 includes an
on-chip phase-lock loop (PLL) which can gener-
ate its requisite 5.12 MHz master clock from a
20 kHz sampling signal.
The CS5317 features two modes of operation
which utilize the internal PLL. The first, termed
Clock Generation 1 (CLKG1), accepts a sam-
pling clock up to 20 kHz at the CLKIN pin and
internally generates the requisite 5.12 MHz clock.
The CS5317 then processes samples updating its
output register at the rate defined at CLKIN, typi-
cally 20 kHz. For a 20 kHz clock input the digital
filter’s 3 dB corner is set at 5.239 kHz, so CLKG1
provides a factor of 2X oversampling at the sys-
tem level (20 kHz is twice the minimum possible
sampling frequency needed to reconstruct a 5
kHz input). The CLKG1 mode is initiated by ty-
ing the MODE input to +5V.
0.1
4
16
9
3
8
6
5
7
F
Source
uP or DSP
Clock
10
Interface
Control
Serial
Data
VD- (clock override mode / CLKOR)
VD+ (clock gen. mode / CLKG1)
F
(clock gen. mode / CLKG2)
0.1
F
10
F
CS5317
7