mk2069-03 Integrated Device Technology, mk2069-03 Datasheet - Page 5

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mk2069-03

Manufacturer Part Number
mk2069-03
Description
Vcxo-based Clock Translator With High Multiplication
Manufacturer
Integrated Device Technology
Datasheet
IDT™ / ICS™ VCXO-BASED CLOCK TRANSLATOR WITH HIGH MULTIPLICATION 5
MK2069-03
VCXO-BASED CLOCK TRANSLATOR WITH HIGH MULTIPLICATION
Application Information
The MK2069-03 is a mixed analog / digital integrated circuit
that is sensitive to PCB (printed circuit board) layout and
external component selection. Used properly, the device will
provide the same high performance expected from a
canned VCXO-based hybrid timing device, but at a lower
cost. To help avoid unexpected problems, the guidance
provided in the sections below should be followed.
Setting VCLK Output Frequency
The frequency of the VCLK output is determined by the
following relationship:
VCLK output frequency range is set by the allowable
frequency range of the external VCXO crystal and by the
internal VCXO divider selections:
A higher crystal frequency will generally produce lower
phase noise and therefore is preferred. A crystal frequency
between 13.5 MHz and 27 MHz is recommended.
Because VCLK is generated by the external crystal, the
tracking range of VCLK in a given configuration is limited by
the pullable range of the crystal. This is guaranteed to be
+/-115 ppm minimum. This tracking range in ppm also
applies to the input clock and all clock outputs if the device
is to remain frequency locked to the input, which is required
f(VCLK)
Where:
Where:
f(VCLK)
FPV Divider = 2 to 65
FV Divider = 1 to 4096
f(VCXO) = F(External Crystal) = 8 to 27 MHz
SV Divider = 1,2,4,6,8,10,12 or 16
FPV Divider = 2 to 65
=
=
FPV Divider
---------------------- -
SV Divider
f VCXO
FV Divider
VCXO AND SYNTHESIZER
MK2069-03
f(ICLK)
REV J 030906

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