mpc9850 Integrated Device Technology, mpc9850 Datasheet - Page 4

• Manufacturer Part Number: mpc9850
• Description: Xtal-input, Lvcmos Input, 8 Lvcmos Output Clock Generator
• Manufacturer: Integrated Device Technology

IDT™ Clock Generator for PowerQUICC III
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MPC9850
Clock Generator for PowerQUICC III
Output Frequency Configuration
used frequencies in PowerQUICC, PowerPC and other
microprocessor systems.
values that will generate those common frequencies. The
MPC9850 can generate numerous other frequencies that
may be useful in specific applications. The output frequency
(f
following equation.
where f
Note that N = 15 is a modified case of the configuration inputs
Power Supply Bypassing
architecture of the MPC9850 supports low noise signal
operation at high frequencies. In order to maintain its superior
signal quality, all V
high-frequency ceramic capacitors connected to GND. If the
spectral frequencies of the internally generated switching
noise on the supply pins cross the series resonant point of an
individual bypass capacitor, its overall impedance begins to
look inductive and thus increases with increasing frequency.
The parallel capacitor combination shown ensures that a low
impedance path to ground exists for frequencies well above
the noise bandwidth.
MPC9850
4
out
The MPC9850 was designed to provide the commonly
This calculation is valid for all values of N from 8 to 126.
The MPC9850 is a mixed analog/digital product. The
) of either Bank A or Bank B may be calculated by the
out
is in MHz and N = 2 * CLK_x[0:5]
DD
pins should be bypassed by
f
out
Table 3
= 2000 / N
V
MR
DD
lists the configuration
t
reset_rel
OPERATION INFORMATION
Figure 2. MR Operation
4
CLK_x[0:5]. To achieve N = 15 CLK_x[0:5] is configured to
00111 or 7.
Crystal Input Operation
Power-Up and MR Operation
length for MR pin. The MR release time is based upon the
power supply being stable and within V
Table 11
configured after release of reset and the outputs will be stable
for use after lock indication is obtained.
TBD
Figure 2
V
DD
for actual parameter values. The MPC9850 may be
Figure 3. V
defines the release time and the minimum pulse
15 Ω
t
reset_pulse
CC
22 µF
Power Supply Bypass
Advanced Clock Drivers Devices
0.1 µF
0.1 µF
Freescale Semiconductor
DD
specifications. See
V
V
DD
DDA
MPC9850
NETCOM
MPC9850