pc87311a National Semiconductor Corporation, pc87311a Datasheet - Page 23

• Manufacturer Part Number: pc87311a
• Description: Pc87311a/pc87312 Superi/otm Ii/iii Floppy Disk Controller With Dual Uarts, Parallel Port, And Ide Interface
• Manufacturer: National Semiconductor Corporation

3 0 FDC Register Description
D7
D6 – D4 Reserved Always 0
D3
D2
D1 D0 Data Rate Select 1 0 These bits indicate the
3 9 CONFIGURATION CONTROL REGISTER (CCR)
Write Only
This is the write-only data rate register commonly used in
PC-AT applications This register is not affected by a soft-
ware reset and is set to 250 kb s after a hardware reset
The data rate of the floppy controller is determined by the
last write to either the CCR or DSR
3 9 1 CCR PC-AT and PS 2 Modes
D7–D2 Reserved Should be set to 0
D1 D0 Data Rate Select 1 0 These bits determine the
3 9 2 CCR Model 30 Mode
D7–D3 Reserved Should be set to 0
D2
D1 D0 Data Rate Select 1 0 These bits determine the
3 10 RESULT PHASE STATUS REGISTERS
The Result Phase of a command contains bytes that hold
status information The format of these bytes is described
below Do not confuse these status bytes with the Main
Status Register which is a read only register that is always
valid The Result Phase status registers are read from the
Data Register (FIFO) only during the Result Phase of certain
commands (see Section 4 1 Command Set Summary) The
status of each register bit is indicated when the bit is a 1
3 10 1 Status Register 0 (ST0)
DESC
RESET
COND
DESC
RESET
COND
DESC
RESET
COND
Disk Changed Active low status of DSKCHG disk
interface input During power down this bit will be
invalid if it is read by the software
DMA Enable Active high status of the DMAEN bit
in the DOR
No Precompensation Active high status of the
NOPRE bit in the CCR
status of the DRATE 1 0 bits programmed through
the DSR CCR
data rate of the floppy controller See Table 3-6 for
the appropriate values
No Precompensation This bit can be set by soft-
ware but it has no functionality It can be read by bit
D2 of the DIR when in the Model 30 register mode
Unaffected by a software reset
data rate of the floppy controller See Table 3-6 for
the appropriate values
N A
N A
D7
D7
0
0
D7
IC
0
N A
D6
N A
0
D6
0
D6
IC
0
N A
D5
N A
0
D5
0
D5
SE
0
N A
D4
0
N A
D4
0
D4
EC
0
N A
D3
0
N A
D3
0
D3
NOPRE
0
0
N A
N A
D2
D2
0
HDS
D2
0
DRATE1
DRATE1
D1
1
D1
1
DS1
D1
0
(Continued)
DRATE0
DRATE0
D0
D0
DS0
0
0
D0
0
23
D7–D6 Interrupt Code
D5
D4
D3
D2
D1 D0 Drive Select 1 0 These two binary encoded bits
3 10 2 Status Register 1 (ST1)
D7
D6
D5
D4
D3
D2
D1
DESC
RESET
COND
00
01
10
11
Seek End Seek Relative Seek or Recalibrate
command completed by the controller (Used during
a Sense Interrupt command )
Equipment Check After a Recalibrate command
Track 0 signal failed to occur (Used during Sense
Interrupt command )
Not Used Always 0
Head Select Indicates the active high status of the
HDSEL pin at the end of the Execution Phase
indicate the logical drive selected at the end of the
Execution Phase
00
01
10
11
End of Track Controller transferred the last byte of
the last sector without the TC pin becoming active
The last sector is the End of Track sector number
programmed in the Command Phase
Not Used Always 0
CRC Error If this bit is set and bit 5 of ST2 is clear
then there was a CRC error in the Address Field of
the correct sector If bit 5 of ST2 is also set then
there was a CRC error in the Data Field
Overrun Controller was not serviced by the mP
soon enough during a data transfer in the Execution
Phase For read operations indicates a data over-
run For write operations indicates a data underrun
Not Used Always 0
No Data Three possible problems
1 Controller cannot find the sector specified in the
2 Controller cannot read any Address Fields with-
3 Controller cannot find starting sector during exe-
Not Writable Write Protect pin is active when a
Write or Format command is issued
Command Phase during the execution of a Read
Write Scan or Verify command An address
mark was found however so it is not a blank disk
out a CRC error during a Read ID command
cution of Read A Track command
e
e
e
e
e
e
e
e
D7
ET
0
Drive 0 selected
Drive 1 selected
Drive 2 selected
Drive 3 selected
Normal Termination of Command
Abnormal Termination of Command Execu-
tion of command was started but was not
successfully completed
Invalid Command Issued Command issued
was not recognized as a valid command
Internal drive ready status changed state dur-
ing the drive polling mode Only occurs after a
hardware or software reset
D6
0
0
CE
D5
0
OR
D4
0
D3
0
0
ND
D2
0
NW
D1
0
MA
D0
0