pc87311a National Semiconductor Corporation, pc87311a Datasheet - Page 16

• Manufacturer Part Number: pc87311a
• Description: Pc87311a/pc87312 Superi/otm Ii/iii Floppy Disk Controller With Dual Uarts, Parallel Port, And Ide Interface
• Manufacturer: National Semiconductor Corporation

2 0 Configuration Registers
2 5 2 Function Address Register (FAR Index
This register selects the ISA I O address range to which
each peripheral function will respond
Bits 0 1 These bits select the parallel port address as
Note The interrupt assigned to this address can be changed to IRQ7 by
setting Bit 3 of the power and test register
Bits 2–5 These bits determine which ISA I O address range
Note COM3 and COM4 addresses are determined by Bits 6 and 7
Bits 6 7 These bits select the addresses that will be used
2 5 3 Power and Test Register (PTR Index
This register determines several power down features the
power down method used when the power down pin
Bit
1
0
0
1
1
TABLE 2-7 Address Selection for COM3 and COM4
Bit 7
0
0
1
1
Bit 3
Bit
TABLE 2-6a COM Port Selection for UART1
TABLE 2-6b COM Port Selection for UART2
Bit 5
0
0
1
0
1
0
0
1
1
shown in Table 2-5
for COM3 and COM4 (see Table 2-7)
0
0
1
1
is associated with each UART (see Tables 2-6a
2-6b)
TABLE 2-5 Parallel Port Addresses
LPT2 (378 – 37F)
LPT1 (3BC – 3BE)
LPT3 (278 – 27F)
Reserved
Bit 6
FAR
0
1
0
1
Address
FAR
Parallel
Port
Bit 2
0
1
0
1
COM3 IRQ4
Bit 4
3E8 – Fh
338 – Fh
2E8 – Fh
0
1
0
1
220 – 7h
IRQ5 (Note)
(CTR4
TRI-STATE
Interrupt
IRQ7
IRQ5
AT
e
1 (3F8-F)
2 (2F8-F)
3 (Table 2 – 7)
4 (Table 2 – 7)
0)
UART1
COM
COM4 IRQ3
UART2
COM
e
2E8 – Fh
238 – Fh
2E0 – 7h
228 – Fh
(CTR4
TRI-STATE
(Continued)
e
Interrupt
1
2
3
4
2)
IRQ7
IRQ7
IRQ7
1)
XT
e
0)
16
(PWDN) is asserted (crystal and clocks vs clocks only)
whether hardware power down is enabled and provides a
bit for software power down of all enabled functions It se-
lects whether IRQ7 or IRQ5 is associated with LPT2 It puts
the enabled UARTs into their test mode Independent of this
register the floppy disk controller can enter low power mode
via the Mode Command or the Data Rate Select Register
Bit 0 Setting this bit causes all enabled functions to be
Bit 1 When the Power Down pin or Bit 0 is asserted this bit
Bit 2 Setting this bit enables the chip select function of the
Bit 3 Setting this bit associates the parallel port with IRQ7
Bit 4 Setting this bit puts UART1 into a test mode which
Bit 5 Setting this bit puts UART2 into a test mode which
Bit 6 Setting this bit to a one prevents all further write ac-
Bit 7 This bit determines the operating mode of the parallel
2 6 POWER DOWN OPTIONS
There are various methods for entering the power down
mode All methods result in one of three possible modes
This section associates the methods of entering the power
down with the resulting mode
Mode 1 The internal clock stops for a specific function (i e
UART1 and or UART2 and or FDC)
This mode is entered by
A Clearing the FER bit for the specific function that will be
B Also during reset by setting certain CFG0 – 4 pins See
powered down See Section 2 5 1 FER bits 1 – 3
Table 2-1
powered down If the crystal power down option is
selected (see Bit 1) the crystal will also be powered
down All register data is retained when the crystal or
clocks are stopped
determines whether the enabled functions will have
their internal clocks stopped (Bit 1
nal crystal (Bit 1
crystal is the lowest power consumption state of the
part However if the crystal is stopped a finite
amount of time ( E 8 ms) will be required for crystal
stabilization once the Power Down pin (PWDN) or
Bit 0 is deasserted If all internal clocks are stopped
but the crystal continues to oscillate no stabilization
period is required after the Power Down pin or Bit 0 is
deasserted
PWDN CSOUT pin Resetting this bit enables the
power down function of this pin
when the address for the parallel port is 378 – 37Fh
(LPT2) This bit is a ‘‘don’t care’’ when the parallel
port address is 3BC – 3BEh (LPT1) or 278 – 27Fh
(LPT3)
causes its Baudout clock to be present on its SOUT1
pin if the Line Control Register bit 7 is set to 1
causes its Baudout clock to be present on its SOUT2
pin if the Line Control Register bit 7 is set to 1
cesses to the Configuration Registers Once this bit is
set by software it can only be cleared by a hardware
reset After the initial hardware reset this bit is zero
port If PTR7 is low then the parallel port is in Com-
patible Mode If PTR7 is high then the parallel port is
in Extended Mode This bit will be the inverse of the
state of the POE pin immediately after reset has oc-
curred PTR7 can be programmed at any time
e
1) will be stopped Stopping the
e
0) or the exter-