pc87307 National Semiconductor Corporation, pc87307 Datasheet - Page 150

• Manufacturer Part Number: pc87307
• Description: Plug And Play Compatible And Pc97 Compliant Superi/o
• Manufacturer: National Semiconductor Corporation

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Bit 0 - Delta Clear to Send (DCTS)
Bit 1 - Delta Data Set Ready (DDSR)
Bit 2 - Trailing Edge Ring Indicate (TERI)
Bit 3 - Delta Data Carrier Detect (DDCD)
Bit 4 - Clear To Send (CTS)
Bit 5 - Data Set Ready (DSR)
Bit 6 - Ring Indicate (RI)
Bit 7 - Data Carrier Detect (DCD)
X
7
Set to 1, when the CTS input signal changes state.
This bit is cleared upon read.
Set to 1, when the DSR input signal changes state.
This bit is cleared upon read
Set to 1, when the RI input signal changes state from
low to high.
This bit is cleared upon read
Set to 1, when the DCD input signal changes state.
1 - DCD signal state changed.
This bit returns the inverse of the CTS input signal.
This bit returns the inverse of the DSR input signal.
This bit returns the inverse of the RI input signal.
This bit returns the inverse of the DCD input signal.
DCD
X
6
RI
FIGURE 7-16. MSR Register Bitmap
X
5
DSR
X
4
CTS
0
3
DDCD
0
2
TERI
0
1
DDSR
0
0
Reset
Required
DCTS
UART1 and UART2 (with IR) (Logical Devices 5 and 6)
Register (MSR)
Modem Status
Offset 06h
Bank 0,
150
7.11.10 Scratchpad Register (SPR), Bank 0, Offset 07h
This register shares a common address with the ASCR Register.
In Non-Extended mode, this is a scratch register (as in the
16550) for temporary data storage.
7.11.11 Auxiliary Status and Control Register (ASCR),
This register shares a common address with the previous
one (SCR).
This register is accessed when the Extended mode of op-
eration is selected. The definition of the bits in this case is
dependent upon the mode selected in the MCR register,
bits 7 through 5. This register is cleared upon hardware re-
set or when the operational mode changes. Bits 2 and 6 are
cleared when the transmitter is “soft reset”. Bits 0,1,4 and 5
are cleared when the receiver is “soft reset”.
Bit 0 - RX_FIFO Time-Out (RXF_TOUT)
Bit 1 -Reserved
0
0
7
7
This bit is read only and set to 1 when an RX_FIFO tim-
eout occurs. It is cleared when a character is read from
the RX_FIFO.
Read/Write 0.
Reserved
0
6
6
Bank 0, Offset 07h
0
TXUR
FIGURE 7-18. ASCR Register Bitmap
5
5
FIGURE 7-17. SPR Register Bitmap
RXACT
0
4
4
RXWDG
0
0
3
3
Non-Extended Modes
Reserved
0
Extended Modes
2
2
Scratch Data
0
0
S_EOT
1
1
Reserved
0
0
0
Reset
Required
RXF_TOUT
Reset
Required
Scratchpad Register
Register (ASCR)
Auxiliary Status
Offset 07h
Offset 07h
Bank 0,
Bank 0,
(SCR)