ics9148-53 ETC-unknow, ics9148-53 Datasheet
ics9148-53
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ics9148-53 Summary of contents
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... Frequency Generator & Integrated Buffers for Mother Boards General Description 2 Block Diagram Power Groups 9148-53 Rev C 08/14/98 ICS9148-53 Features Pin Configuration 48-Pin SSOP Pentium is a trademark of Intel Corporation trademark of Philips Corporation ICS reserves the right to make changes in the device data identified in this publication without further notice ...
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... ICS9148-53 Pin Descriptions PIN NUMBER PIN NAME 1 VDD1 REF0 2 FS3 3,9,16,22,27, GND 33,39, VDD2 PCICLK_F FS1 PCICLK0 8 FS2 1, 2 10, 11, 12, 13, 47 PCICLK(1:5) 14 VDD5 15 BUFFERIN CPU_STOP# 17 SDRAM 11 1 PCI_STOP# 18 SDRAM 10 28, 29, 31, 32, 34, SDRAM (0:9) 35,37,38 1 AGP_STOP# 20 SDRAM9 1 PD# 21 SDRAM8 19,30,36 VDD3 23 SDATA 24 SCLK ...
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... PCICLK_F, PCICLK CPUCLK REF, 48MHz (0:5) Outputs and SDRAM Stopped Low Running Running Running Running Running Running Stopped Low Running Running Running Running ICS9148-53 Pin 21 PD# (INPUT) SDRAM 8 (OUTPUT) Crystal VCO AGP(1:2) OSC Running Running Running Running Running Running Running Running Running ...
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... ICS9148-53 Functionality DD FS3 FS2 FS1 CPU,SDRAM FS0 (MHZ) PCI (MHZ) AGP (MHZ) 1 133 44.33 0 124 41.33 1 150 50 0 140 46 ...
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... General I C serial interface information Clock Generator Address (7 bits bits dummy ACK A(6:0) & R/W# command code D2 (H) Clock Generator Address (7 bits) Byte Count ACK A(6:0) & R/W# Readback D3 ( bits dummy ACK Byte count 2 ACK 2 ICS9148-53 ACK ...
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... ICS9148-53 Serial Configuration Command Bitmap Bit Description 0 - ±0.25% Spread Spectrum Modulation Bit ±0.6% Spread Spectrum Modulation Bit (2, 6:4) CPU CLKs PCI CLKs AGP CLKs 1111 133 1110 124 1101 150 1100 140 1011 105 1010 112 1001 115 Bit 1000 120 ...
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... Bit 1 Bit Pin # Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ICS9148-53 Pin # PWD cription - 1 (Reserved (Act/Inact (Reserved (Act/Inact (Act/Inact (Act/Inact) ...
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... ICS9148-53 CPU_STOP# Timing Diagram ...
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... PCI_STOP# Timing Diagram ICS9148-53 ...
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... ICS9148-53 AGP_STOP# Timing Diagram ...
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... Shared Pin Operation - Input/Output Pins Fig. 1 ICS9148-53 ...
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... ICS9148-53 Fig. 2a Fig. 2b ...
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... DDL CONDITIONS pF; 66.8 MHz 1 66/100 MHz; CPU leads 1 83/75 MHz; CPU leads 1 66.8 MHz; AGP Leads 1 83.3 MHz; AGP Leads 1 100 MHz; AGP Leads T ICS9148-53 MIN TYP MAX UNITS -0 ...
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... ICS9148-53 Electrical Characteristics - CPU 70C 3.3 V +/-5 DDL PARAMETER SYMBOL Output High Voltage V OH2A Output Low Voltage V OL2A Output High Current I OH2A Output Low Current I OL2A 1 Rise Time t r2A 1 Fall Time t f2A 1 Duty Cycle d t2A 1 Skew t sk2A 1 Jitter, One Sigma ...
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... 1.5 V, synchronous 1.5 V, asynchronous 1.5 V, synchronous 1.5 V, asynchronous T ICS9148-53 MIN TYP MAX UNITS 2 0.2 0.4 V - 200 500 ps MIN TYP MAX UNITS 2.4 ...
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... ICS9148-53 Electrical Characteristics - AGP 70C 3.3 V +/-5 DDL PARAMETER SYMBOL Output High Voltage V OH1 Output Low Voltage V OL1 Output High Current I OH1 Output Low Current I OL1 1 Rise Time Fall Time Duty Cycle Skew t sk1 1 Jitter, One Sigma ...
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... ICS9148-53 ...
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... ICS9148-53 SYMBOL COMMON DIMENSIONS MIN. NOM. A .095 .101 A1 .008 .012 A2 .088 .090 B .008 .010 C .005 D See Variations E .292 .296 e 0.025 BSC H .400 .406 h .010 .013 L .024 .032 N See Variations 0° 5° X .085 .093 Ordering Information ICS9148F-53 ICS XXXX F - PPP VARIATIONS MAX. ...