isl8118 Intersil Corporation, isl8118 Datasheet
isl8118
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isl8118 Summary of contents
Page 1
... Data Sheet 3.3V to 20V, Single-Phase PWM Controller with Integrated 2A/4A MOSFET Drivers The ISL8118 is a single-phase PWM controller featuring an input voltage range of +3.3V to +20V and integrated MOSFET drivers. Utilizing voltage-mode operation with input voltage feed-forward compensation, the ISL8118 maintains a constant loop gain, providing optimal transient response for applications with a wide input operating voltage range ...
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Block Diagram REFIN REFOUT MARGIN OFSP VOLTAGE MARGINING OFSN OTA SS FB COMP VCC 800mV PGOOD COMP VSENSP VSENSN UNITY GAIN DIFF AMP VDIFF PGDLY PGOOD EN VCC POWER-ON REFERENCE RESET (POR 0.591V REF SOFT-START ...
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... OFSN SS EXDRV ISL8118 BOOT BOOT VCC PVCC BOOT R TSOC TSOC C TSOC TGATE LX BGATE PGND R BSOC BSOC ISL8118 C BSOC COMP VDIFF VSENSP VSENSN GND GND C HFIN C BIN C BOOT Q1 L OUT C HFOUT C BOUT Q2 10Ω ...
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... ISL8118 BOOT BOOT F1 VCC PVCC BOOT R TSOC TSOC C TSOC TGATE LX BGATE PGND R BSOC BSOC ISL8118 C BSOC COMP VDIFF VCC VSENSP VSENSN GND GND C HFIN C BIN C BOOT Q1 L OUT C BOUT C Q2 HFOUT ...
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... OFSN OFSN ISL8118 BOOT VCC PVCC BOOT R TSOC TSOC C TSOC TGATE LX BGATE PGND R BSOC BSOC ISL8118 C BSOC COMP VDIFF VSENSP VSENSN EXDRV GND GND C HFIN C BIN C BOOT Q1 L OUT C HFOUT ...
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... OSC_MIN Minimum Usable VFF Voltage POWER-ON RESET Rising VCC Threshold POR Falling VCC Threshold POR 6 ISL8118 Thermal Information Thermal Resistance (Notes 1, 2) QFN Package . . . . . . . . . . . . . . . . . . Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . 150°C Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150° 0.3V Maximum Lead Temperature (Soldering 10s 300°C ...
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... VSENSN Disable Voltage V VSEN_DIS OPERATIONAL TRANSCONDUCTANCE AMPLIFIER (OTA) DC Gain Drive Capability PWM Maximum Duty Cycle Minimum Duty Cycle GATE DRIVERS TGATE Source Resistance R 7 ISL8118 TEST CONDITIONS VCC_H PVCC_R PVCC_F PVCC_H VFF_R VFF_F VFF_H T = 0°C to 70° -40°C to 85°C ...
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... Internal Reference Maximum Margining Voltage of V Internal Reference Margining Transfer Ratio N Positive Margining Threshold MARGIN Negative Margining Threshold MARGIN Tri-state Input Level MARGIN 8 ISL8118 TEST CONDITIONS V = 2.5V, PVCC = 5.0V TGATE TGATE-LX 500mA Sink Current, PVCC = 5.0V TGATE V = 2.5V, PVCC = 5.0V TGATE TGATE-LX 500mA Source Current, PVCC = 5.0V ...
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... OFSP and OFSN pins translates to a -200mV offset of the system reference. VCC (Pin 8, Analog Circuit Bias) This pin provides power for the ISL8118 analog circuitry. The pin should be connected to a 2.9V to 5.6V bias through an RC filter from PVCC to prevent noise injection into the analog circuitry ...
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... F capacitor developed across the bottom side MOSFET when on. The µ sinking current limit is set the nominal sourcing limit in ISL8118. An initial ~120ns blanking period is used to eliminate the sampling error due to switching noise before the current is measured. FSET (Pin 24) This pin provides oscillator switching frequency adjustment ...
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... The POR function activates the internal 38µA OTA which begins charging the external capacitor (C target voltage of VCC. The ISL8118’s soft-start logic continues to charge the SS pin until the voltage on COMP exceeds the bottom of the oscillator ramp, at which point, the driver outputs are enabled, with the bottom side MOSFET first being held low for 200ns to provide for charging of the bootstrap capacitor ...
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... Number of Bottom side MOSFETs = B 12 ISL8118 The ISL8118’s sinking current limit is set to the same voltage as its sourcing limit. In sinking applications, when the voltage across the MOSFET is greater than the voltage developed across the resistor (R triggered. To avoid non-synchronous operation at light load, the peak to peak output inductor ripple current should not be greater than twice of the sinking current limit ...
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... See the ISL6605 datasheet for specification parameters that are not defined in the current ISL8118 electrical specifications table. TO GND) A 1-2Ω resistor is recommended series with the T bootstrap diode when using VCCs above 5.0V to prevent the bootstrap capacitor from overcharging due to the negative swing of the trailing edge of the LX node ...
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... MAXIMUM of MARG 1V across R . MARG The OFS pins are completely independent and can be set to different margining levels. The maximum usable reference voltage for the ISL8118 is VCC - 1.8V, and should not be exceeded when using the margining functionality, i.e, V < VCC - 1.8V. REF_MARG V R REF MARG • ...
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... Figure 8 should be located as close together as possible. Please note that the capacitors C and C O Locate the ISL8118 within 3 inches of the MOSFETs, Q1 and Q2. The circuit traces for the MOSFETs’ gate and source connections from the ISL8118 must be sized to handle peak current. ...
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... FIGURE 10. VOLTAGE-MODE BUCK CONVERTER The compensation network consists of the error amplifier at the IN (internal to the ISL8118) and the external R components. The goal of the compensation network is to provide a closed loop transfer function with high 0dB crossing frequency (F phase margin (better than 45°). Phase margin is the difference between the closed loop phase at F The equations that follow relate the compensation network’ ...
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... C SEN time constant does not reduce the overall phase margin of the design, typically this 10x switching frequency of the regulator. As the ISL8118 supports 100% duty cycle, d equals 1. The ISL8118 also uses MAX feed-forward compensation, as such V 0.16 multiplied by the voltage at the VFF pin. When tieing ...
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... Given a sufficiently fast control loop design, the ISL8118 will provide either 0% or 100% duty cycle in response to a load transient. The response time is the time required to slew the inductor current from an initial current value to the transient current level ...
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... The TPS series available from AVX, and the 593D series from Sprague are both surge current tested. MOSFET Selection/Considerations The ISL8118 requires 2 N-Channel power MOSFETs. These should be selected based upon r DS(ON) requirements, and thermal management requirements. In high-current applications, the MOSFET power dissipation, package selection and heatsink are the dominant design factors ...
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... CORNER REF. OPTION 4X BOTTOM VIEW SECTION "C-C" TERMINAL TIP FOR ODD TERMINAL/SIDE FOR EVEN TERMINAL/SIDE 20 ISL8118 L28.5x5 28 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220VHHD-1 ISSUE SYMBOL 0. ...