isl2671286 Intersil Corporation, isl2671286 Datasheet
isl2671286
Related parts for isl2671286
isl2671286 Summary of contents
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... Auto Power-Down mode. These features make the ISL2671286 an excellent solution for remote industrial sensors and battery-powered instruments. The ISL2671286 is available SOIC package and is specified for operation over the industrial temperature range of –40°C to +85°C. VREF ...
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... RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL2671286. For more information on MSL please see Tech Brief TB363. 2 ...
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... THD Total Harmonic Distortion SINAD Signal-to (Noise + Distortion) Ratio SFDR Spurious Free Dynamic Range 3 ISL2671286 Thermal Information Thermal Resistance (Typical SOIC Package (Notes 4, 5 PDIP Package (Notes Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+100°C Pb-Free Reflow Profile ...
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... Conversion Time CONV t Delay Time, DCLOCK↓ to DOUT Data Valid dDO t Delay Time, CS/SHDN↑ to DOUT Hi-Z DIS t Delay Time, DCLOCK↓ to DOUT Enable EN 4 ISL2671286 = +5V 12.5kHz, f REF SAMPLE TEST CONDITIONS CS/SHDN = VCC t ≥ 640µs, f ≤ 25kHz CYC CLK = 80µs, f ...
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... SMPL (MSB) Note: (2) After completing the data transfer, additional clocks applied while CS/SHDN is low will result in indefinite transmission of zeros 5 ISL2671286 = 200kHz , unless otherwise noted. Typical values are at T (Continued) TEST CONDITIONS CLOAD = 100pF See test circuits; Figure 4 See test circuits; Figure 4 See operating sequence ...
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... DCLOCK t EN DOUT VOL = 0.4V VIH = 2.4V CS/SHDN t DIS DOUT 10% FIGURE 5. TIMING PARAMETER DEFINITIONS 6 ISL2671286 VIL = 0.8V DCLOCK t hDO DOUT VOH = VDD - 0.2V VIL = 0.8V DCLOCK t hDO DOUT VOL = 0.4V 50% CS/SHDN t SUCS DCLOCK 50% 50% CS/SHDN t CSD DCLOCK 50% FN7863.0 November 1, 2011 ...
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... REFERENCE VOLTAGE (V) FIGURE 8. CHANGE IN OFFSET vs REFERENCE VOLTAGE 0.5 0.4 0.3 0.2 CHANGE IN DNL (LSB) 0.1 0.0 -0.1 CHANGE IN INL (LSB) -0 REFERENCE VOLTAGE (V) FIGURE 10. CHANGE IN INTEGRAL LINEARITY AND DIFFERENTIAL LINEARITY vs REFERENCE VOLTAGE 7 ISL2671286 +25°C, +VCC = V A REF 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 -55 FIGURE 7. REFERENCE CURRENT vs TEMPERATURE 1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1 -55 FIGURE 9. CHANGE IN OFFSET vs TEMPERATURE ...
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... FREQUENCY (kHz) FIGURE 14. SIGNAL-TO-(NOISE + DISTORTION) vs FREQUENCY -40 -35 -30 -25 -20 INPUT LEVEL (dB) FIGURE 16. SIGNAL-TO-(NOISE + DISTORTION) vs INPUT LEVEL 8 ISL2671286 +25°C, +VCC = 10.0 0 FIGURE 13. DIFFERENTIAL LINEARITY ERROR vs CODE 100 ...
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... TEMPERATURE (°C) FIGURE 20. CHANGE IN GAIN vs TEMPERATURE 450 400 f = 12.5kHz SAMPLE 350 300 250 200 150 100 -55 -35 - TEMPERATURE (°C) FIGURE 22. SUPPLY CURRENT vs TEMPERATURE 9 ISL2671286 +25°C, +VCC = -10 -20 -30 -40 -50 -60 -70 -80 - FIGURE 19. POWER SUPPLY REJECTION vs RIPPLE FREQUENCY 3.0 2.5 2.0 1.5 1 ...
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... Typical Performance Characteristics otherwise specified. (Continued) 3.0 2.5 2.0 1.5 1.0 0.5 0.0 3.00 3.25 3.50 3.75 4.00 4.25 4.50 4.75 5.00 5.25 5.50 SUPPLY VOLTAGE (V) FIGURE 24. DIGITAL INPUT LINE THRESHOLD vs SUPPLY VOLTAGE 10 ISL2671286 +25°C, +VCC = REF SAMPLE 10.0 1.0 0.1 0.01 -55 -35 -15 FIGURE 25. INPUT LEAKAGE CURRENT vs TEMPERATURE = 12.5kHz unless CLK SAMPLE 105 TEMPERATURE (°C) FN7863.0 November 1, 2011 ...
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... VREF FIGURE 26. SAR ADC ARCHITECTURAL BLOCK DIAGRAM ADC Transfer Function The output coding for the ISL2671286 is straight binary. The first code transition occurs at successive LSB values (i.e., 1 LSB, 2 LSB, and so on). The LSB size is VREF/4096. The ideal transfer characteristic of the ISL2671286 is shown in Figure 27. ...
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... IN 10 100 Reduced Reference Operation The ISL2671286 exhibits good linearity and gain over a wide range of reference voltages (see Figures 10 and 11). When operating at low values of VREF, offset errors and noise must be considered because of the reduced LSB size. Input errors can have a larger impact on performance when ...
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... GND pin on the ISL2671286 as possible. Avoid running digital lines under the device, as this couples noise onto the die. The analog ground plane should be allowed to run under the ISL2671286 to avoid noise coupling. Power supply lines to the device should use as large a trace as possible, to provide low impedance paths and to reduce the effects of glitches on the power supply line ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see 14 ISL2671286 www.intersil.com/askourstaff http://rel.intersil.com/reports/search.php For additional products, see www ...
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... Package Outline Drawing M8.15 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE Rev 3, 3/11 INDEX AREA TOP VIEW 5.00 (0.197) 4.80 (0.189) 1.27 (0.050) 0.51(0.020) 0.33(0.013) SIDE VIEW “A 15 ISL2671286 DETAIL "A" 6.20 (0.244) 5.80 (0.228) 4.00 (0.157) 3.80 (0.150) 8° 0° 1 SEATING PLANE 1.75 (0.069) 2 1.35 (0.053) 3 -C- 4 0.25(0.010) 0.10(0.004) ...