rs5c338a RICOH Co.,Ltd., rs5c338a Datasheet - Page 32

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rs5c338a

Manufacturer Part Number
rs5c338a
Description
3-wire Serial Interface Real-time Clock Ics With Voltage Monitoring Function
Manufacturer
RICOH Co.,Ltd.
Datasheet

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32
R
3. Oscillation Halt Sensing and Supply Voltage Monitoring
The oscillation halt sensing circuit is configured to record a halt in the oscillation of 32.768-kHz clock pulses. The
supply voltage monitoring circuit is configured to record a drop in supply voltage below a threshold voltage of 2.1 or
1.6 volts. For these functions, the real-time clock has two flag bits (i.e. the XSTP bit for the former and the VDET bit
for the latter) in which 1 is set once and this setting is maintained until 0 is written.
When the XSTP bit is set to 1 for the oscillation halt sensing circuit, the VDET bit is reset to 0 for the supply voltage
monitoring circuit. The relationship between the XSTP and VDET bits is shown in the table below.
The Oscillation halt sensing circuit operates only when the CE pin is Low. The sensing result is maintained after
the CE pin changes from “L” to “H” (See “6.4 Connection of CE Pin”).
When the XSTP bit is set to 1 in the control register 2, the (0), F
CT1, CT0, VDSL, VDET, SCRATCH, CLEN1, CTFG, WAFG, and DAFG bits are reset to 0 in the oscillation
adjustment register, the control register 1, and the control register 2. When the CE pin is “H” at power on from 0
volts, the XSTP bit is undefined, and the above bits are undefined (See “6.4 Connection of CE Pin”). The XSTP bit is
also set to 1 at power-on from 0 volts. Note that the XSTP bit may be locked to 0 and the internal register broken
upon instantaneous power-down.
Oscillation by 32.768-kHz clock pulses
×
XSTP
5C338A
Supply voltage monitoring (VDET)
0
0
1
Oscillation halt sensing (XSTP)
Normal voltage detector
VDET
*
0
1
Supply voltage
No drop in supply voltage below threshold voltage and no halt in oscillation
Drop in supply voltage below threshold voltage and no halt in oscillation
Halt on oscillation
Internal initialization
period
(1 to 2 seconds)
Conditions of supply voltage and oscillation
Setting XSTP and
VDET bits to 0
6
to F
0
, WALE, DALE, 12/24, CLEN2, TEST, CT2,
Setting VDET bit to 0
Threshold voltage (2.1 or 1.6 volts)
Setting XSTP and
VDET bits to 0

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