upd78f0103 Renesas Electronics Corporation., upd78f0103 Datasheet - Page 472

• Manufacturer Part Number: upd78f0103
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

472
Standby
function
Reset
function
Function
OSTC:
Oscillation
stabilization time
counter status
register
OSTS: Oscillation
stabilization time
select register
STOP mode
setting and
operating
statuses
LVI circuit
internal reset
Reset timing due
to watchdog timer
overflow
RESF: Reset
control flag
register
Details of
Function
−
After the above time has elapsed, the bits are set to 1 in order from MOST11
and remain 1.
If the STOP mode is entered and then released while the Ring-OSC clock is
being used as the CPU clock, set the oscillation stabilization time as follows.
The X1 oscillation stabilization time counter counts only during the oscillation
stabilization time set by OSTS. Therefore, note that only the statuses during
the oscillation stabilization time set by OSTS are set to OSTC after STOP
mode has been released.
The wait time when STOP mode is released does not include the time after
STOP mode release until clock oscillation starts (“a” below) regardless of
whether STOP mode is released by RESET input or interrupt generation.
To set the STOP mode when the X1 input clock is used as the CPU clock, set
OSTS before executing the STOP instruction.
Execute the OSTS setting after confirming that the oscillation stabilization time
has elapsed as expected in the OSTC.
If the STOP mode is entered and then released while the Ring-OSC clock is
being used as the CPU clock, set the oscillation stabilization time as follows.
The X1 oscillation stabilization time counter counts only during the oscillation
stabilization time set by OSTS. Therefore, note that only the statuses during
the oscillation stabilization time set by OSTS are set to OSTC after STOP
mode has been released.
The wait time when STOP mode is released does not include the time after
STOP mode release until clock oscillation starts (“a” below) regardless of
whether STOP mode is released by RESET input or interrupt generation.
Because the interrupt request signal is used to clear the standby mode, if
there is an interrupt source with the interrupt request flag set and the interrupt
mask flag reset, the standby mode is immediately cleared if set. Thus, the
STOP mode is reset to the HALT mode immediately after execution of the
STOP instruction and the system returns to the operating mode as soon as the
wait time set using the oscillation stabilization time select register (OSTS) has
elapsed.
For an external reset, input a low level for 10
During reset input, the X1 input clock and Ring-OSC clock stop oscillating.
When the STOP mode is released by a reset, the STOP mode contents are
held during reset input. However, the port pins become high-impedance,
except for P130, which is set to low-level output.
An LVI circuit internal reset does not reset the LVI circuit.
A watchdog timer internal reset resets the watchdog timer.
Do not read data via a 1-bit memory manipulation instruction.
• Desired OSTC oscillation stabilization time ≤ Oscillation stabilization time
• Desired OSTC oscillation stabilization time ≤ Oscillation stabilization time
APPENDIX D LIST OF CAUTIONS
set by OSTS
set by OSTS
User’s Manual U15836EJ5V0UD
Cautions
µ
s or more to the RESET pin.
p.308
p.308
p.299
p.299
p.299
p.300
p.300
p.300
p.300
p.304
p.308
p.309
p.310
p.314
(18/20)
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