upd78f0103 Renesas Electronics Corporation., upd78f0103 Datasheet - Page 467

• Manufacturer Part Number: upd78f0103
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

Serial
interface
UART0
Serial
interface
UART6
Function
ASIS0:
Asynchronous
serial interface
reception error
status register 0
BRGC0: Baud
rate generator
control register 0
POWER0, TXE0,
RXE0: Bits 7, 6, 5
of ASIM0
UART mode
UART
transmission
UART reception
Error of baud rate
Permissible baud
rate range during
reception
UART mode
Details of
Function
The operation of the PE0 bit differs depending on the set values of the PS01
and PS00 bits of asynchronous serial interface operation mode register 0
(ASIM0).
Only the first bit of the receive data is checked as the stop bit, regardless of
the number of stop bits.
If an overrun error occurs, the next receive data is not written to receive buffer
register 0 (RXB0) but discarded.
If data is read from ASIS0, a wait cycle is generated. For details, see
CHAPTER 29 CAUTIONS FOR WAIT.
When the Ring-OSC clock is selected as the clock to be supplied to the CPU,
the clock of the Ring-OSC oscillator is divided and supplied as the count clock.
If the base clock is the Ring-OSC clock, the operation of serial interface
UART0 is not guaranteed.
Make sure that bit 6 (TXE0) and bit 5 (RXE0) of the ASIM0 register = 0 when
rewriting the MDL04 to MDL00 bits.
The baud rate value is the output clock of the 5-bit counter divided by 2.
Clear POWER0 to 0 after clearing TXE0 and RXE0 to 0 to set the operation
stop mode.
To start the operation, set POWER0 to 1, and then set TXE0 and RXE0 to 1.
Take relationship with the other party of communication when setting the port
mode register and port register.
After transmit data is written to TXS0, do not write the next transmit data
before the transmission completion interrupt signal (INTST0) is generated.
Be sure to read receive buffer register 0 (RXB0) even if a reception error
occurs. Otherwise, an overrun error will occur when the next data is received,
and the reception error status will persist.
Reception is always performed with the “number of stop bits = 1”. The second
stop bit is ignored.
Be sure to read asynchronous serial interface reception error status register 0
(ASIS0) before reading RXB0.
Keep the baud rate error during transmission to within the permissible error
range at the reception destination.
Make sure that the baud rate error during reception satisfies the range shown
in (4) Permissible baud rate range during reception.
Make sure that the baud rate error during reception is within the permissible
error range, by using the calculation expression shown below.
The T
the reception side. To use this function, the reception side must be ready for
reception of inverted data.
If clock supply to serial interface UART6 is not stopped (e.g., in the HALT
mode), normal operation continues. If clock supply to serial interface UART6
is stopped (e.g., in the STOP mode), each register stops operating, and holds
the value immediately before clock supply was stopped. The T
holds the value immediately before clock supply was stopped and outputs it.
However, the operation is not guaranteed after clock supply is resumed.
Therefore, reset the circuit so that POWER6 = 0, RXE6 = 0, and TXE6 = 0.
APPENDIX D LIST OF CAUTIONS
X
D6 output inversion function inverts only the transmission side and not
User’s Manual U15836EJ5V0UD
Cautions
X
D6 pin also
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