upd78f0103 Renesas Electronics Corporation., upd78f0103 Datasheet - Page 460

• Manufacturer Part Number: upd78f0103
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

460
16-bit timer/
event
counter 00
(TM00)
Function
One-shot pulse
output: Software
trigger
One-shot pulse
output: External
trigger
Timer start errors
16-bit timer
capture/compare
registers 000,
010 setting
Capture register
data retention
timing
Valid edge
setting
One-shot pulse
output: Software
trigger
One-shot pulse
output: External
trigger
One-shot pulse
output function
Operation of
OVF00 flag
Details of
Function
Do not set the CR000 and CR010 registers to 0000H.
16-bit timer counter 00 starts operating as soon as the TMC003 and TMC002
bits are set to a value other than 00 (operation stop mode).
Even if the external trigger is generated again while the one-shot pulse is
being output, it is ignored.
Do not set the CR000 and CR010 registers to 0000H.
16-bit timer counter 00 starts operating as soon as the TMC002 and TMC003
bits are set to a value other than 00 (operation stop mode).
An error of up to one clock may occur in the time required for a match signal to
be generated after timer start. This is because 16-bit timer counter 00 (TM00)
is started asynchronously to the count clock.
In the mode in which clear & start occurs on match between TM00 and
CR000, set 16-bit timer capture/compare registers 000, 010 (CR000, CR010)
to other than 0000H. This means a 1-pulse count operation cannot be
performed when 16-bit timer/event counter 00 is used as an external event
counter.
The values of 16-bit timer capture/compare registers 000 and 010 (CR000 and
CR010) are not guaranteed after 16-bit timer/event counter 00 has been
stopped.
Set the valid edge of the TI000 pin after setting bits 2 and 3 (TMC002 and
TMC003) of 16-bit timer mode control register 00 (TMC00) to 0, 0,
respectively, and then stopping timer operation. The valid edge is set using
bits 4 and 5 (ES000 and ES001) of prescaler mode register 00 (PRM00).
When a one-shot pulse is output, do not set the OSPT00 bit to 1. Do not
output the one-shot pulse again until INTTM000, which occurs upon a match
with the CR000 register, or INTTM010, which occurs upon a match with the
CR010 register, occurs.
If the external trigger occurs again while a one-shot pulse is output, it is
ignored.
When using the one-shot pulse output of 16-bit timer/event counter 00 with a
software trigger, do not change the level of the TI000 pin or its alternate
function port pin.
Because the external trigger is valid even in this case, the timer is cleared and
started even at the level of the TI000 pin or its alternate function port pin,
resulting in the output of a pulse at an undesired timing.
The OVF00 flag is also set to 1 in the following case.
If any of the following modes: the mode in which clear & start occurs on a
match between TM00 and CR000, the mode in which clear & start occurs on a
TI000 valid edge, or the free-running mode, is selected
→ CR000 is set to FFFFH.
→ TM00 is counted up from FFFFH to 0000H.
Even if the OVF00 flag is cleared before the next count clock (before TM00
becomes 0001H) after the occurrence of TM00 overflow, the OVF00 flag is re-
set newly and clear is disabled.
APPENDIX D LIST OF CAUTIONS
User’s Manual U15836EJ5V0UD
Cautions
p.141
p.142
p.142
p.143
p.144
p.145
p.145
p.145
p.145
p.145
p.145
p.145
p.146
p.146
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