upd78f0103 Renesas Electronics Corporation., upd78f0103 Datasheet - Page 264

• Manufacturer Part Number: upd78f0103
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

(4) Permissible baud rate range during reception
264
The permissible error from the baud rate at the transmission destination during reception is shown below.
Caution Make sure that the baud rate error during reception is within the permissible error range, by
As shown in Figure 12-26, the latch timing of the receive data is determined by the counter set by baud rate
generator control register 6 (BRGC6) after the start bit has been detected. If the last data (stop bit) meets this
latch timing, the data can be correctly received.
Assuming that 11-bit data is received, the theoretical values can be calculated as follows.
Maximum permissible
FL = (Brate)
Minimum permissible data frame length: FLmin = 11
Minimum permissible
Data frame length
Brate: Baud rate of UART6
k:
FL:
Margin of latch timing: 2 clocks
data frame length
data frame length
using the calculation expression shown below.
of UART6
Set value of BRGC6
1-bit data length
1
Figure 12-26. Permissible Baud Rate Range During Reception
Latch timing
Start bit
Start bit
Start bit
CHAPTER 12 SERIAL INTERFACE UART6
User’s Manual U15836EJ5V0UD
Bit 0
Bit 0
FL
Bit 0
Bit 1
Bit 1
Bit 1
FL
1 data frame (11
FLmin
k
2k
2
FLmax
Bit 7
FL =
Bit 7
FL)
Bit 7
21k + 2
2k
Parity bit
Parity bit
Parity bit
FL
Stop bit
Stop bit
Stop bit