upd78f0103 Renesas Electronics Corporation., upd78f0103 Datasheet - Page 216
upd78f0103
Manufacturer Part Number
upd78f0103
Description
8-bit Single-chip Microcontrollers
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.UPD78F0103.pdf
(485 pages)
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(3) Baud rate generator control register 0 (BRGC0)
216
Address: FF71H After reset: 1FH R/W
BRGC0
Notes 1.
Symbol
This register selects the base clock of serial interface UART0 and the division value of the 5-bit counter.
BRGC0 can be set by an 8-bit memory manipulation instruction.
RESET input sets this register to 1FH.
2.
Be sure to set the base clock so that the following condition is satisfied.
Note the following points when selecting the TM50 output as the base clock.
• V
• V
• V
• V
• PWM mode (TMC506 = 1)
• Mode in which the base clock is cleared and started upon a match of TM50 and CR50 (TMC506 = 0)
It is not necessary to enable the TO50 pin as a timer output pin in any mode.
MDL04
TPS01
TPS01
Start the operation of 8-bit timer/event counter 50 first and then set the base clock to make the duty =
50%.
Start the operation of 8-bit timer/event counter 50 first and then enable the timer F/F inversion
operation (TMC501 = 1).
7
0
0
0
0
1
1
1
1
1
1
DD
DD
DD
DD
0
0
1
1
•
•
•
•
•
CHAPTER 11 SERIAL INTERFACE UART0 (
Figure 11-4. Format of Baud Rate Generator Control Register 0 (BRGC0)
= 4.0 to 5.5 V: Base clock ≤ 10 MHz
= 3.3 to 4.0 V: Base clock ≤ 8.38 MHz
= 2.7 to 3.3 V: Base clock ≤ 5 MHz
= 2.5 to 2.7 V: Base clock ≤ 2.5 MHz
MDL03
TPS00
TPS00
0
1
0
1
6
0
1
1
1
•
•
•
•
•
1
1
1
1
1
1
TM50 output
f
f
f
X
X
X
/2 (5 MHz)
/2
/2
MDL02
3
5
(1.25 MHz)
(312.5 kHz)
5
0
×
0
0
0
•
•
•
•
•
0
0
1
1
1
1
User’s Manual U15836EJ5V0UD
Note 2
MDL04
MDL01
4
×
0
0
1
1
1
0
0
1
1
•
•
•
•
•
Base clock (f
µ
MDL00
MDL03
PD780102, 780103, 78F0103 ONLY)
3
×
0
1
0
0
1
0
1
0
1
•
•
•
•
•
XCLK0
) selection
10
26
27
28
29
30
31
k
×
8
9
•
•
•
•
•
MDL02
2
Setting prohibited
f
f
f
f
f
f
f
f
f
XCLK0
XCLK0
XCLK0
XCLK0
XCLK0
XCLK0
XCLK0
XCLK0
XCLK0
Selection of 5-bit counter
Note 1
/8
/9
/10
/26
/27
/28
/29
/30
/31
MDL01
output clock
1
•
•
•
•
•
MDL00
0
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