cy23fp12 Cypress Semiconductor Corporation., cy23fp12 Datasheet
cy23fp12
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cy23fp12 Summary of contents
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... These parameters are critical for reference clock distribution in systems using high-performance ASICs and microprocessors. The CY23FP12 is fully programmable via volume or prototype programmers enabling the user to define an appli- cation-specific Zero Delay Buffer with customized input and output dividers, feedback topology (internal/external), output inversions, and output drive strengths ...
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... Bank A. LVTTL Clock output, Bank A. LVTTL Clock output, Bank A. POWER Ground for Bank A. LVTTL Clock output, Bank A. LVTTL CLock output, Bank A. LVTTL PLL feedback input. LVTTL Reference select input. REFSEL = 0, REF1 is selected. REFSEL = 1, REF2 is selected. CY23FP12 Description Page [+] Feedback ...
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... CLKB2 and CLKB3 will become complimentary pairs. Document #: 38-07246 Rev. *E /1,/2,/3,/4, /x,/2x /1,/2,/3,/4, /x,/2x Output /1,/2,/3,/4, /x,/2x Function PLL Select /1,/2,/3,/4, /x,/2x Matrix /1,/2,/3,/4, /x,/2x /1,/2,/3,/4, /x,/2x Figure 1. Basic PLL Block Diagram Description CY23FP12 CLKB5 CLKB4 CLKB3 CLKB2 CLKB1 CLKB0 CLKA5 CLKA4 CLKA3 CLKA2 CLKA1 CLKA0 Default +16 mA +16 mA Enable Enable Non-invert Non-invert Non-invert ...
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... CLKB3 and CLKB2 pair. Please refer to Table 3 for a list of divider values. CLKB10 Source Independently selects one out of the eight possible output dividers that will connect to the CLKB1 and CLKB0 pair. Please refer to Table 3 for a list of divider values. Document #: 38-07246 Rev. *E Description Description CY23FP12 Default Non-invert Enable Enable External Default ...
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... CY23FP12 Frequency Calculation The CY23FP12 is an extremely flexible clock buffer with up to twelve individual outputs, generated from an integrated PLL. [1] There are four variables used to determine the final output frequency ...
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... ATES UL–94 Flammability Rating FIT Failure in Time T Power-up time for all reach PU DD minimum specified voltage (power ramps must be monotonic) DC Electrical Specifications for CY23FP12SC/I Commercial/Industrial Temperature Devices Parameter Description V Core Supply Voltage DDC Bank A, Bank B DDA DDB Supply Voltage ...
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... Outputs @200 MHz, tracking skew not included All outputs equally loaded Same frequency Different frequency Different voltage, same frequency Measured at V /2, REF to FBK DD Measured Bank A and B same frequency Bank A and B different frequency CY23FP12 Min. Typ. Max. Unit 10 200 MHz 1 V/ ...
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... Input reference clock @ < 50-KHz modulation with ±3.75% spread Stable power supply, valid clock at REF Max loop delay for PLL Lock (stable frequency) Max loop delay to meet Tracking Skew Spec 1.4V 3.3V 0. CY23FP12 Min. Typ. Max. Unit 200 ps 1 Page ...
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... CY23FP12OCT 28-pin SSOP – Tape and Reel CY23FP12OI 28-pin SSOP CY23FP12OIT 28-pin SSOP – Tape and Reel CY3672 Development Kit CY3692 CY23FP12S Socket (Label CY3672 ADP006) Lead-free CY23FP12OXC 28-pin SSOP CY23FP12OXCT 28-pin SSOP – Tape and Reel CY23FP12OXI 28-pin SSOP CY23FP12OXIT 28-pin SSOP – ...
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... Document History Page Document Title: CY23FP12 200-MHz Field Programmable Zero Delay Buffer Document Number: 38-07246 Orig. of REV. ECN NO. Issue Date Change ** 115158 07/03/02 *A 121880 12/14/02 *B 124523 03/19/03 *C 126938 06/16/03 *D 129364 09/10/03 *E 299718 See ECN Document #: 38-07246 Rev. *E Description of Change HWT New data sheet RBI Power-up requirements added to Absolute Maximum Ratings information ...