cy23fp12-002 Cypress Semiconductor Corporation., cy23fp12-002 Datasheet

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... VSSC Cypress Semiconductor Corporation Document #: 38-07644 Rev. ** Functional Description The CY23FP12-002 is a pre-programmed version of the CY23FP12. It features a high-performance fully field-program- mable 200 MHz zero delay buffer designed for high speed clock distribution. The integrated PLL is designed for low jitter and optimized for noise rejection. These parameters are critical for reference clock distribution in systems using high- performance ASICs and microprocessors ...

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... Bank A. LVTTL Clock output, Bank A. LVTTL Clock output, Bank A. POWER Ground for Bank A. LVTTL Clock output, Bank A. LVTTL CLock output, Bank A. LVTTL PLL feedback input. LVTTL Reference select input. REFSEL = 0, REF1 is selected. REFSEL = 1, REF2 is selected. CY23FP12-002 Description Page [+] Feedback ...

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... CLKB2 and CLKB3 will become complimentary pairs. Document #: 38-07644 Rev. ** /1,/2,/3,/4, /x,/2x /1,/2,/3,/4, /x,/2x Output /1,/2,/3,/4, /x,/2x Function PLL Select /1,/2,/3,/4, /x,/2x Matrix /1,/2,/3,/4, /x,/2x /1,/2,/3,/4, /x,/2x Figure 1. Basic PLL Block Diagram Description CY23FP12-002 CLKB5 CLKB4 CLKB3 CLKB2 CLKB1 CLKB0 CLKA5 CLKA4 CLKA3 CLKA2 CLKA1 CLKA0 Default +20 mA +20 mA Enable Enable Non-invert Non-invert Non-invert ...

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... CLKB3 and CLKB2 pair. Please refer to Table 3 for a list of divider values. CLKB10 Source Independently selects one out of the eight possible output dividers that will connect to the CLKB1 and CLKB0 pair. Please refer to Table 3 for a list of divider values. Document #: 38-07644 Rev. ** CY23FP12-002 Description Description Default Non-invert ...

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... CY23FP12-002 Frequency Calculation 200 33.3 200 50 The CY23FP12-002 is an extremely flexible clock buffer with up to twelve individual outputs, generated from an integrated 200 25 PLL. 200 50 There are four variables used to determine the final output frequency. These are the input Reference Frequency M, the N ...

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... Total Functional Gate Count ATES UL–94 Flammability Rating FIT Failure in Time T Power-up time for all reach PU DD minimum specified voltage (power ramps must be monotonic) DC Electrical Specifications for CY23FP12-002SC/I Parameter Description V Core Supply Voltage DDC Bank A, Bank B DDA DDB Supply Voltage [3] ...

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... Switching Characteristics for CY23FP12-002SC/I Parameter Description [6] Reference Frequency Reference Edge Rate Reference Duty Cycle [7] t Output Frequency 1 [5] Duty Cycle [5] t Rise Time 3 [5] t Fall Time 4 [8,9] TTB Total Timing Budget, Bank A and B same frequency Total Timing Budget, Bank A and B different frequency ...

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... Switching Characteristics for CY23FP12-002SC/I Parameter Description t Tracking Skew tsk [5] t PLL Lock Time LOCK T Inserted Loop Delay LD Switching Waveforms Duty Cycle Timing 1.4V 1.4V All Outputs Rise/Fall Time 2.0V 2.0V OUTPUT 0. Output-Output Skew 1.4V OUTPUT 1.4V OUTPUT t 5 Input-Output Propagation Delay INPUT ...

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... Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CLK OUT C LOAD Package Type Commercial, 0°C to 70°C Commercial,0°C to 70°C Industrial, –40°C to 85°C Industrial, –40°C to 85°C CY23FP12-002 Operating Range 51-85079-*C Page [+] Feedback ...

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... Document History Page Document Title: CY23FP12-002 200-MHz Field Programmable Zero Delay Buffer Document Number: 38-07644 Orig. of REV. ECN NO. Issue Date Change ** 206761 See ECN Document #: 38-07644 Rev. ** Description of Change RGL New Data Sheet CY23FP12-002 Page [+] Feedback ...