spd6722qcce Intel Corporation, spd6722qcce Datasheet - Page 58
spd6722qcce
Manufacturer Part Number
spd6722qcce
Description
Isa-to-pc-card Pcmcia Controllers
Manufacturer
Intel Corporation
Datasheet
1.SPD6722QCCE.pdf
(138 pages)
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PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers
8.0
8.1
58
Register Name: I/O Window Control
Index: 07h
Register
Select 1
Timing
RW:0
Bit 7
Compatibility
I/O Window Mapping Registers
The I/O windows must never include 3E0h and 3E1h.
I/O Window Control
Bit 0 — I/O Window 0 Size
When bit 1 below is ‘0’, this bit determines the size of the data path to I/O Window 0. When bit 1 is
‘1’, this bit is ignored.
Bit 1 — Auto-Size I/O Window 0
This bit determines the data path to I/O Window 0. Note that when this bit is ‘1’, the -IOIS16 signal
(see
Bit 3 — Timing Register Select 0
This bit determines the access timing specification for I/O Window 0 (see
page
RW:0
Bit 6
Bit
Table 2 on page
84).
0
1
0
1
0
1
I/O Window 0 Size (see bit 0 above) determines the data path to I/O Window 0.
The data path to I/O Window 0 will be determined based on -IOIS16 returned by the card.
8-bit data path to I/O Window 0.
16-bit data path to I/O Window 0.
Accesses made with timing specified in Timing Set 0.
Accesses made with timing specified in Timing Set 1.
Auto-Size I/O
Window 1
RW:0
Bit 5
20) determines the width of the data path to the card.
I/O Window 1
RW:0
Bit 4
Size
Register
Select 0
Timing
RW:0
Bit 3
Compatibility
RW:0
Bit 2
Bit
Register Compatibility Type: 365
Auto-Size I/O
Window 0
“Setup Timing 0–1” on
RW:0
Bit 1
Register Per: socket
I/O Window 0
Datasheet
RW:0
Bit 0
Size
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