LTC3546 Linear Technology, LTC3546 Datasheet - Page 23

• Manufacturer Part Number: LTC3546
• Description: 3A/1A or 2A/2A Configurable Step-Down DC/DC Regulator
• Manufacturer: Linear Technology

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APPLICATIONS INFORMATION
operating frequency of 1.5MHz and assumes roughly a
300mA/A load step.
The closest values are 22μF and 68μF .
The output voltages can now be programmed by choos-
ing the values of R1, R2, R3, and R4. To maintain high
effi ciency, the current in these resistors should be kept
small. Choosing 2μA with the 0.6V feedback voltages
makes R2 and R4 equal to 300k. A close standard 1%
resistor is 301k. This then makes R1 = 300k. A close
standard 1% is 301k. R3 then equals 600k. A close 1%
resistor is 604k.
The compensation should be optimized for these com-
ponents by examining the load step response but a good
place to start for the LTC3546 is with a 13kΩ and 1000pF
fi lter on both I
need to be increased depending on the actual transient
during a load step.
The PGOOD pin is a common drain output and requires a
pull-up resistor. A 100k resistor is used for adequate speed.
Figure 9 shows a complete schematic for this design.
Board Layout Considerations
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3546. These items are also illustrated graphically
in the layout diagram of Figure 7. Check the following in
your layout.
1. Make sure SW1, SW2A, SW2B and SW1D are connected
on the PC board through a wide piece of copper.
C
C
OUT
OU
T T
1
1
=
=
22
22
A
A
µF
µF
TH1
• .
• .
0 8
2 5
and I
A
A
•
•
TH2
300
300
. The output capacitor may
A
A
280
875
mA
mA
mA
mA
• .
• .
0 8
2 5
A
A
=
=
64 2
20 5
.
.
µF
µF
2. All, or part, of C
3. Are the respective C
4. The resistor divider, R1 and R2, must be connected
5. When using the R
6. Keep sensitive components away from the SW pins.
7. A ground plane is preferred, but if not available, keep
8. Flood all unused areas on all layers with copper. Flooding
on the same side of the PC board as the chip and as
close to the chip as possible, where the SW traces will go
directly under the capacitor. C
to the internal power MOSFETs and their drivers.
plate of C
plate of C
plate of C
PGND2.
between the (+) plate of C
minated near GNDA. The resistor divider R3 and R4,
must be connected between the (+) plate of C
the ground connection terminated to the GNDA pin.
The feedback signals V
away from noise components and traces, such as the
SW lines, and its trace should be minimized.
of the resistor should be terminated to the GNDA pin.
When using the internal PLL, the ground connection of
the R-C compensation network should be terminated
to the GNDA pin.
The input capacitor C
C
R3, R4, R
the SW traces and the inductors L1 and L2.
the signal and power grounds segregated with small
signal components returning to the SGND pin at one
point which is then connected to the PGND1/PGND2/
PGND1D/GNDD pins.
with copper will reduce the temperature rise of power
components. These copper areas should be connected
to the Exposed Pad (Pin 29).
FF1
, C
FF2
OUT1
OUT2
IN
, C
ITH1
should also return current to PGND1 and
ITH1
and R
returns current to PGND1, and the (–)
returns current to the PGND2. The (–)
IN
, and C
FREQ
should connect from Pin 9 to Pin 14
OUT
ITH2
IN
resistor, the ground connection
FB1
, L closely connected? The (–)
, the compensation capacitors
ITH2
should be routed away from
OUT1
and V
IN
and all resistors R1, R2,
provides the AC current
and a ground line ter-
FB2
LTC3546
should be routed
OUT2
23
3546fb
and