LTC1705 Linear Technology, LTC1705 Datasheet - Page 8

• Manufacturer Part Number: LTC1705
• Description: Dual 550kHz Synchronous Switching Regulator Controller
• Manufacturer: Linear Technology

PI FU CTIO S
LTC1705
RUN/SS (Pin 9): SoftStart. Pulling RUN/SS to GND exter-
nally shuts down the LTC1705 and turns off all the external
MOSFET switches. The quiescent supply current drops
below 100 A. A capacitor from RUN/SS to GND controls
the turn on time and rate of rise of the core and I/O output
voltages at power up. An internal 3 A current source pull-
up at RUN/SS sets the turn-on time at approximately
300ms/ F.
COMPC (Pin 10): Core Controller Loop Compensation.
The COMPC pin is connected directly to the output of the
Core controller’s error amplifier and the input of the PWM
comparator. Use an RC network between the COMPC pin
and the FBC pin to compensate the feedback loop for
optimum transient response.
FBC (Pin 11): Core Controller Feedback Input. Connect the
loop compensation network for the core controller to FBC.
FBC internally connects to the VID resistor network to set
the Core output voltage.
GND (Pin 12): Signal Ground. All internal low power
circuitry returns to the GND pin. Connect to a low imped-
ance ground, separated from the PGND node. All feed-
back, compensation and softstart connections should
return to GND. GND and PGND should connect only at a
single point, near the PGND pin and the negative plate of
the V
SENSEC (Pin 13): Core Controller Output Sense. Connect
to V
VID0 to VID4 (Pins 14 to 18): VID Programming Inputs.
These are logic inputs that set the output voltage at the
Core supply to a preprogrammed value (see Table 1). VID4
is the MSB, VID0 is the LSB. The codes selected by the VID
inputs correspond to the Intel Mobile VID specification.
Any VID code transition forces PGOOD to go low for 20 s.
Each VID pin includes an on-chip 30k pull-up resistor in
series with a diode (see Block Diagram).
V
except the output drivers are powered from this pin.
Connect V
to GND with at least a 10 F capacitor in close proximity to
the LTC1705.
8
CC
U
OUTC
(Pin 19): Power Supply Input. All internal circuits
IN
bypass capacitor.
.
CC
U
to a low-noise 5V supply and bypass the pin
U
FBIO (Pin 20): I/O Controller Feedback Input. Connect
FBIO through a resistor divider network to V
output voltage. Also, connect the loop compensation
network for the I/O controller to FBIO.
COMPIO (Pin 21): I/O Controller Loop Compensation. See
COMPC.
PGOOD (Pin 22): Power Good. PGOOD is an open-drain
logic output. PGOOD pulls low if any of the three supply
outputs are out of regulation (see Electrical Characteris-
tics table for Core, I/O and CLK thresholds). An external
pull-up resistor is required at PGOOD to allow it to swing
positive.
V
output node of the internal linear clock supply regulator.
V
the CPU CLK supply. Bypass V
capacitor to GND (refer to the V
section). If RUN/SS goes low, the V
down.
V
terminal to the internal linear CLK supply regulator. Con-
nect V
can be connected to the 5V supply, but the efficiency of the
V
capacitor to GND.
SWIO (Pin 25): I/O Controller Switching Node. See SWC.
TGIO (Pin 26): I/O Controller Top Gate Drive. See TGC.
TGIO is designed to typically drive up to 2,000pF of gate
capacitance.
BOOSTIO (Pin 27): I/O Controller Top Gate Driver Power.
See BOOSTC.
BGIO (Pin 28): I/O Controller Bottom Gate Drive. See BGC.
BGIO is designed to typically drive up to 2,000pF of gate
capacitance.
OUTCLK
OUTCLK
INCLK
OUTCLK
INCLK
(Pin 24): Clock Supply Input. V
provides up to 150mA at the 2.5V output to power
regulator is reduced. Bypass V
(Pin 23): Clock Supply Output. V
to a 3.3V supply to maximize efficiency. V
OUTCLK
OUTCLK
CLK
with at least a 2.2 F
Linear Regulator
INCLK
INCLK
regulator shuts
OUTIO
OUTCLK
with a 10 F
is the input
to set the
is the
INCLK