HEF4013BT,652 NXP Semiconductors, HEF4013BT,652 Datasheet - Page 9
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HEF4013BT,652
Manufacturer Part Number
HEF4013BT,652
Description
IC FLIP FLOP DUAL D TYPE 14SOIC
Manufacturer
NXP Semiconductors
Series
4000Br
Type
D-Typer
Specifications of HEF4013BT,652
Package / Case
14-SOIC (3.9mm Width), 14-SOL
Function
Set(Preset) and Reset
Output Type
Differential
Number Of Elements
2
Number Of Bits Per Element
1
Frequency - Clock
40MHz
Trigger Type
Positive Edge
Current - Output High, Low
3.4mA, 3.4mA
Voltage - Supply
3 V ~ 15 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Number Of Circuits
2
Logic Family
HE4000B
Logic Type
D-Type Flip-Flop
Polarity
Inverting/Non-Inverting
Input Type
Single-Ended
Propagation Delay Time
90 ns
High Level Output Current
- 4.2 mA
Low Level Output Current
4.2 mA
Supply Voltage (max)
15 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Supply Voltage (min)
3 V
Technology
CMOS
Number Of Bits
2
Number Of Elements
2
Clock-edge Trigger Type
Positive-Edge
Operating Supply Voltage (typ)
3.3/5/9/12V
Package Type
SO
Frequency (max)
40MHz
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
15V
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
14
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Delay Time - Propagation
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-1685-5
933372660652
HEF4013BTD
933372660652
HEF4013BTD
Philips Semiconductors
AC CHARACTERISTICS
Clock input rise and fall times (t
The upper limits on t
individual data sheets it is recommended that input rise and fall times be less than 15 s for V
V
Output transition times (t
V
Temperature coefficient (typical values)
Propagation delays
Output transition times
Input capacitance (digital inputs)
Maximum input capacitance C
January 1995
t
t
SYMBOL
DD
SS
THL
TLH
= 0; T
= 10 V; 1 s for V
amb
output transition times
= 25 C; C
HIGH to LOW
LOW to HIGH
PARAMETER
r
and t
DD
L
= 15 V.
= 50 pF; input transition times
f
TLH
vary widely from device to device and with supply voltage. Unless otherwise specified in the
+0.35%/ C
+0.35%/ C
, t
I
= 7.5 pF
THL
r
, t
)
f
)
5
10
15
5
10
15
V
(V)
DD
MIN.
60
30
20
60
30
20
20 ns.
9
TYP.
120
60
40
120
60
40
MAX.
ns
ns
ns
ns
ns
ns
UNIT
10 ns + (1.0 ns/pF) C
9 ns + (0.42 ns/pF) C
6 ns + (0.28 ns/pF) C
10 ns + (1.0 ns/pF) C
9 ns + (0.42 ns/pF) C
6 ns + (0.28 ns/pF) C
Family Specifications
TYPICAL EXTRAPOLATION
DD
FORMULA
= 5 V; 4 s for
L
L
L
L
L
L