AD9517-2 Analog Devices, Inc., AD9517-2 Datasheet - Page 77
AD9517-2
Manufacturer Part Number
AD9517-2
Description
12-output Clock Generator With Integrated 2.2 Ghz Vco
Manufacturer
Analog Devices, Inc.
Datasheet
1.AD9517-2.pdf
(80 pages)
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Reg.
Addr
(Hex) Bit(s) Name
1E1
1E1
Table 60. System
Reg.
Addr
(Hex) Bit(s) Name
230
230
230
Table 61. Update All Registers
Reg.
Addr
(Hex) Bit(s) Name
232
<1>
<0>
<0>
<2>
<1>
<0>
Select VCO or CLK
Bypass VCO Divider
Update All
Registers
Power-Down SYNC
Power-Down Distribution Reference
Soft SYNC
Description
This bit must be set to 1 to transfer the contents of the buffer registers into the active registers. This happens
on the next SCLK rising edge. This bit is self-clearing; that is, it does not have to be set back to 0.
<0> = 1 (self-clearing); update all active registers to the contents of the buffer registers.
Description
Select either the VCO or the CLK as the input to VCO divider.
<1> = 0; select external CLK as input to VCO divider.
<1> = 1; select VCO as input to VCO divider; cannot bypass VCO divider when this is selected.
Bypass or use the VCO divider.
<0> = 0; use VCO divider.
<0> = 1; bypass VCO divider; cannot select VCO as input when this is selected.
Description
Power down the SYNC function.
<2> = 0; normal operation of the SYNC function.
<2> = 1; power-down SYNC circuitry.
Power down the reference for distribution section.
<1> = 0; normal operation of the reference for the distribution section.
<1> = 1; power down the reference for the distribution section.
The soft SYNC bit works the same as the SYNC pin, except that the polarity of the bit
is reversed. That is, a high level forces selected channels into a predetermined static
state, and a 1-to-0 transition triggers a SYNC.
<0> = 0; same as SYNC high.
<0> = 1; same as SYNC low.
Rev. 0 | Page 77 of 80
AD9517-2
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