MT16HTF12864AY-53EC2 Micron, MT16HTF12864AY-53EC2 Datasheet - Page 22

• Manufacturer Part Number: MT16HTF12864AY-53EC2
• Description: DRAM Chip, 512MB, 1GB, 2GB (x64, DR) PC2-3200, PC2-4200, 240-Pin DDR2 SDRAM UDIMM
• Manufacturer: Micron

Table 16: DDR2 I
Notes: 1–5; notes appear on page 28. Values shown for DDR2 SDRAM components only.
pdf: 09005aef80f09084, source: 09005aef80f09068
HTF16C64_128_256x64AG.fm - Rev. B 8/04 EN
PARAMETER/CONDITION
Operating one device bank active-precharge current;
t
valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING.
Operating one device bank active-read-precharge current;
IOUT = 0mA; BL = 4, CL = CL(I
(I
inputs are SWITCHING; Data pattern is same as I
Precharge power-down current;
All device banks idle;
are STABLE; Data bus inputs are FLOATING.
Precharge quiet standby current;
All device banks idle;
bus inputs are STABLE; Data bus inputs are FLOATING.
Precharge standby current;
All device banks idle;
bus inputs are SWITCHING; Data bus inputs are SWITCHING.
Active power-down current;
All device banks open;
address bus inputs are STABLE; Data bus inputs are FLOATING.
Active standby current;
All device banks open;
S# is HIGH between valid commands; Other control and address bus inputs are
SWITCHING; Data bus inputs are SWITCHING.
Operating burst write current;
All device banks open, Continuous burst writes; BL = 4, CL = CL (I
(I
commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING.
Operating burst read current;
All device banks open, Continuous burst reads, I
t
valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING.
Burst refresh current;
t
between valid commands; Other control and address bus inputs are SWITCHING; Data bus
inputs are SWITCHING.
Self refresh current;
CK and CK# at 0V; CKE ≤ 0.2V; Other control and address bus inputs are FLOATING; Data
bus inputs are FLOATING.
Operating device bank interleave read current;
All device banks interleaving reads, I
t
S# is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs;
Data bus inputs are SWITCHING; See I
NOTE:
CK =
CK =
CK =
CK (I
DD
DD
a: Value calculated as one module rank in this operating condition, and all other module ranks in I
b: Value calculated reflects all module ranks in this operating condition.
),
),
DD
t
t
t
t
t
RCD =
RAS =
CK (I
CK (I
CK (I
);
t
CK =
DD
DD
DD
t
t
RAS MAX (I
),
RCD (I
),
); Refresh command at every
t
t
t
RC =
RAS =
CK (I
DD
DD
t
t
t
t
RC (I
); CKE is HIGH, S# is HIGH between valid commands; Address bus
CK =
CK =
CK =
t
t
t
RAS MAX (I
),
CK =
CK =
DD
DD
t
RC =
DD
),
t
t
t
CK (I
CK (I
CK (I
t
t
),
DD
t
CK (I
CK(I
Specifications and Conditions – 1GB
RP =
t
t
RAS =
), AL = 0;
RC(I
DD
DD
DD
DD
PC2-3200, PC2-4200, 240-Pin DDR2 SDRAM UDIMM
DD
DD
t
); CKE is LOW; Other control and address bus inputs
); CKE is HIGH, S# is HIGH; Other control and address
); CKE is HIGH, S# is HIGH; Other control and address
RP (I
DD
),
OUT
); CKE is LOW; Other control and
),
DD
t
t
),
RAS =
RAS MIN (I
t
RP =
7 Conditions for detail.
DD
= 0mA; BL = 4, CL = CL (I
t
RRD =
t
CK =
); CKE is HIGH, S# is HIGH between valid
t
RFC (I
t
t
RP (I
RAS MAX (I
t
t
CK (I
DD
OUT
RRD(I
DD
DD
DD
4W.
) interval; CKE is HIGH, S# is HIGH
); CKE is HIGH, S# is HIGH between
= 0mA; BL = 4, CL = CL (I
DD
); CKE is HIGH, S# is HIGH between
DD
),
),
t
DD
RC =
t
RCD =
),
22
t
RP =
t
RC (I
DD
DD
t
RCD(I
), AL =
), AL = 0;
t
DD
RP(I
),
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Fast PDN Exit
MR[12] = 0
Slow PDN Exit
MR[12] = 1
DD
DD
t
RAS =
t
512MB, 1GB, 2GB (x64, DR)
); CKE is HIGH,
); CKE is HIGH,
RCD (I
DD
t
CK =
), AL = 0;
t
RAS MIN
DD
t
CK
)-1 x
SYMBOL -53E
I
I
I
I
I
I
I
DD
DD
DD
DD
DD
DD
DD
I
I
I
I
I
DD
DD
DD
DD
DD
4W
2Q
2N
3N
2P
3P
4R
5
6
0
1
7
©2004 Micron Technology, Inc. All rights reserved.
a
a
b
b
a
b
b
a
b
b
b
a
DD
1,320
1,240
2,720
1,960
680
760
560
560
400
640
80
96
80
2
P
(CKE LOW) mode.
1,040
2,640
1,880
-40E UNITS
640
720
400
480
320
480
960
80
96
80
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA