LM3S1937-IBZ50 Luminary Micro, Inc, LM3S1937-IBZ50 Datasheet - Page 282
LM3S1937-IBZ50
Manufacturer Part Number
LM3S1937-IBZ50
Description
Lm3s1937 Arm Microcontroller
Manufacturer
Luminary Micro, Inc
Datasheet
1.LM3S1937-IBZ50.pdf
(524 pages)
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Reset
Reset
Type
Type
Analog-to-Digital Converter (ADC)
ADC Processor Sample Sequence Initiate (ADCPSSI)
Base 0x4003.8000
Offset 0x028
Type WO, reset -
282
Bit/Field
31:4
3
2
1
0
WO
WO
31
15
-
-
Register 9: ADC Processor Sample Sequence Initiate (ADCPSSI), offset 0x028
This register provides a mechanism for application software to initiate sampling in the Sample
Sequencers. Sample sequences can be initiated individually or in any combination. When multiple
sequences are triggered simultaneously, the priority encodings in ADCSSPRI dictate execution
order.
WO
WO
30
14
-
-
reserved
WO
WO
29
13
-
-
Name
SS3
SS2
SS1
SS0
WO
WO
28
12
-
-
WO
WO
27
11
-
-
Type
WO
WO
WO
WO
WO
WO
WO
26
10
-
-
reserved
Reset
WO
WO
25
9
-
-
-
-
-
-
-
Preliminary
WO
WO
24
8
-
-
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
SS3 Initiate
Only a write by software is valid; a read of the register returns no
meaningful data. When set by software, sampling is triggered on Sample
Sequencer 3, assuming the Sequencer is enabled in the ADCACTSS
register.
SS2 Initiate
Only a write by software is valid; a read of the register returns no
meaningful data. When set by software, sampling is triggered on Sample
Sequencer 2, assuming the Sequencer is enabled in the ADCACTSS
register.
SS1 Initiate
Only a write by software is valid; a read of the register returns no
meaningful data. When set by software, sampling is triggered on Sample
Sequencer 1, assuming the Sequencer is enabled in the ADCACTSS
register.
SS0 Initiate
Only a write by software is valid; a read of the register returns no
meaningful data. When set by software, sampling is triggered on Sample
Sequencer 0, assuming the Sequencer is enabled in the ADCACTSS
register.
reserved
WO
WO
23
7
-
-
WO
WO
22
6
-
-
WO
WO
21
5
-
-
WO
WO
20
4
-
-
SS3
WO
WO
19
3
-
-
SS2
WO
WO
18
2
-
-
July 25, 2008
SS1
WO
WO
17
1
-
-
SS0
WO
WO
16
0
-
-
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