LM3S1937-IBZ50 Luminary Micro, Inc, LM3S1937-IBZ50 Datasheet - Page 135
LM3S1937-IBZ50
Manufacturer Part Number
LM3S1937-IBZ50
Description
Lm3s1937 Arm Microcontroller
Manufacturer
Luminary Micro, Inc
Datasheet
1.LM3S1937-IBZ50.pdf
(524 pages)
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Reset
Reset
Type
Type
Hibernation Masked Interrupt Status (HIBMIS)
Base 0x400F.C000
Offset 0x01C
Type RO, reset 0x0000.0000
July 25, 2008
Bit/Field
31:4
3
2
1
0
RO
RO
31
15
0
0
Register 8: Hibernation Masked Interrupt Status (HIBMIS), offset 0x01C
This register is the masked interrupt status for the Hibernation module interrupt sources.
RO
RO
30
14
0
0
RTCALT1
RTCALT0
LOWBAT
reserved
RO
RO
29
13
0
0
EXTW
Name
RO
RO
28
12
0
0
RO
RO
27
11
0
0
Type
RO
RO
RO
RO
RO
RO
RO
26
10
0
0
reserved
0x000.0000
Reset
RO
RO
25
0
9
0
0
0
0
0
Preliminary
RO
RO
24
0
8
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
External Wake-Up Masked Interrupt Status
Low Battery Voltage Masked Interrupt Status
RTC Alert1 Masked Interrupt Status
RTC Alert0 Masked Interrupt Status
reserved
RO
RO
23
0
7
0
RO
RO
22
0
6
0
RO
RO
21
0
5
0
RO
RO
20
0
4
0
LM3S1937 Microcontroller
EXTW
RO
RO
19
0
3
0
LOWBAT
RO
RO
18
0
2
0
RTCALT1
RO
RO
17
0
1
0
RTCALT0
RO
RO
16
0
0
0
135
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