LM3S102 Luminary Micro, Inc, LM3S102 Datasheet - Page 54
LM3S102
Manufacturer Part Number
LM3S102
Description
Lm3s102 Arm Microcontroller
Manufacturer
Luminary Micro, Inc
Datasheet
1.LM3S102.pdf
(330 pages)
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System Control
6.3
Table 6-1. System Control Register Map (Sheet 1 of 2)
54
Device Identification and Capabilities
Local Control
System Control
Offset
0x01C
0x05C
0x000
0x004
0x008
0x010
0x014
0x018
0x030
0x034
0x040
0x044
0x048
0x050
0x054
0x058
0x060
0x064
0x100
0x104
Name
DID0
DID1
DC0
DC1
DC2
DC3
DC4
PBORCTL
LDOPCTL
SRCR0
SRCR1
SRCR2
RIS
IMC
MISC
RESC
RCC
PLLCFG
RCGC0
RCGC1
Register Map
Table 6-1 lists the System Control registers, grouped by function. The offset listed is a
hexadecimal increment to the register’s address, relative to the System Control base address of
0x400FE000.
0x00007FFD
0x07803AC0
0x830001C0
0x00070003
0x00000009
0x00000007
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000001
0x00000000
0x01031011
Reset
-
-
-
-
R/W1C
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Preliminary
RO
RO
RO
RO
RO
RO
RO
RO
RO
Description
Device identification 0
Device identification 1
Device capabilities 0
Device capabilities 1
Device capabilities 2
Device Capabilities 3
Device Capabilities 4
Power-On and Brown-Out Reset Control
LDO Power Control
Software Reset Control 0
Software Reset Control 1
Software Reset Control 2
Raw Interrupt Status
Interrupt Mask Control
Masked Interrupt Status and Clear
Reset Cause
Run-Mode Clock Configuration
XTAL to PLL translation
Run-Mode Clock Gating Control 0
Run-Mode Clock Gating Control 1
July 6, 2006
page
See
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