FDC37B72X SMSC Corporation, FDC37B72X Datasheet - Page 110
FDC37B72X
Manufacturer Part Number
FDC37B72X
Description
128 Pin Enhanced Super I/O Controller
Manufacturer
SMSC Corporation
Datasheet
1.FDC37B72X.pdf
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Access to all other registers is possible without
awakening the part.
accessed during powerdown without changing the
status of the part. A read from these registers will
reflect the true status as shown in the register
description in the FDC description. A write to the
part will result in the part retaining the data and
subsequently reflecting it when the part awakens.
Accessing the part during powerdown may cause
an increase in the power consumption by the part.
The part will revert back to its low power mode
when the access has been completed.
Pin Behavior
This chip is specifically designed for systems in
which power conservation is a primary concern.
This makes the behavior of the pins during
powerdown very important.
These registers can be
110
The pins can be divided into two major categories:
system interface and floppy disk drive interface.
The floppy disk drive pins are disabled so that no
power will be drawn through the part as a result of
any voltage applied to the pin within the part's
power supply range. Most of the system interface
pins are left active to monitor system accesses
that may wake up the part.
System Interface Pins
Table 45 gives the state of the system interface
pins in the powerdown state. Pins unaffected by
the powerdown are labeled "Unchanged". Input
pins are "Disabled" to prevent them from causing
currents internal to the chip when they have
indeterminate input values.
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