UPD16633B NEC, UPD16633B Datasheet

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UPD16633B

Manufacturer Part Number
UPD16633B
Description
312 OUTPUT TFT-LCD SORCE DRIVER COMPATIBLE WITH 64 GRAY SCALES
Manufacturer
NEC
Datasheet
Document No. S13214EJ2V0DS00 (2nd edition)
Date Published July 1998 N CP(K)
Printed in Japan
is based on digital input configured as 6 bits by 6 dots (2 pixels), which can realize a full-color display of 260,000
colors by output of 64 values -corrected by an internal D/A converter and 5-by-2 external power modules. Because
the output dynamic range is as large as 9.8 V
rendered unnecessary. Also, to be able to deal with dot-line inversion when mounted on a single side, this source
driver is equipped with a built-in 6-bit D/A converter circuit whose odd output pins and even output pins respectively
output gray scale voltages of differing polarity. Assuring a maximum clock frequency of 45 MHz when driving at 3.0
V, this driver is applicable to XGA-standard TFT-LCD panels.
FEATURES
• Capable of outputting 64 values by means of 5-by-2 external power modules (10 units) and a D/A converter
• Output dynamic range 9.8 V
• CMOS level input
• Input of 6 bits (gradation data) by 6 dots
• High-speed data transfer: fmax. = 45 MHz (internal data transfer speed when operating at 3.0 V)
• 312 outputs
• Apply for only dot inversion
• Display data inversion function (POL2 terminal.)
• Single bank arrangement is possible (loaded with slim TCP)
ORDERING INFORMATION
The TCP’s external shape is customized. To order your TCP’s external shape, please contact a NEC salesperson.
The PD16633B is a source driver for TFT-LCDs capable of dealing with displays with 64 gray scales. Data input
PD16633BN-
Part Number
(COMPATIBLE WITH 64 GRAY SCALES)
312 OUTPUT TFT-LCD SORCE DRIVER
TCP (TAB package)
P-P
Package
min. (@V
DATA SHEET
DD2
= 10.0 V)
P-P
, level inversion operation of the LCD’s common electrode is
MOS INTEGRATED CIRCUIT
PD16633B
©
1998

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UPD16633B Summary of contents

Page 1

... D/A converter and 5-by-2 external power modules. Because the output dynamic range is as large as 9.8 V rendered unnecessary. Also able to deal with dot-line inversion when mounted on a single side, this source driver is equipped with a built-in 6-bit D/A converter circuit whose odd output pins and even output pins respectively output gray scale voltages of differing polarity ...

Page 2

BLOCK DIAGRAM STHR R/L CLK C C STB POL2 POL ...

Page 3

PIN CONFIGURATION ( PD16633BN- V SS2 V DD2 V SS1 R/L POL STB ...

Page 4

... The display data is input with a width of 36 bits, viz., the gray scale data (6 bits dots (2 pixels LSB MSB X0 X5 These refer to the start pulse input/output pins when driver ICs are connected in cascade. The shift directions of the shift registers are as follows. R STHR input STHL output 1 312 ...

Page 5

Cautions 1. The power start sequence must be V this sequence to shut down. (Simultaneous power application to V possible stabilize the supply voltage, please be sure to insert a 0.47 F bypass capacitor between V -V and ...

Page 6

RELATIONSHIP BETWEEN INPUT DATA AND OUTPUT VOLTAGE VALUE This product incorporates a 6-bit D/A converter whose odd output pins and even output pins output respectively gray scale voltages of differing polarity with respect to the LCD’s counter electrode (common ...

Page 7

... ’ 4 ” Caution Between V and V terminal is connected by using the resistor ( the chip DD2 ’ ...

Page 8

... ” ” Caution Between V and V terminal is connected by using the resistor ( the chip ” ...

Page 9

Ladder Resistance Value ( Reference Value 0 62 Table 1. Resistance values of the resistor strings Resistor Name ...

Page 10

RELATIONSHIP BETWEEN INPUT DATA AND OUTPUT PIN Data format : 6 bits 2 RGBs (6 dots) Input width : 36 bits (2-pixel data) R (Right shift) Output Data ...

Page 11

CAUTIONS ABOUT FRAME INVERSION In the case of dot inversion, n frame last line and (n+1) frame first line is the same polarity. When write the same polarity twice, there are two cases as follows. (1) last line output ...

Page 12

ELECTRIC SPECIFICATION Absolute Maximum Ratings (T = 25° Parameter Symbol Logic Part Supply Voltage V DD1 Driver Part Supply Voltage V DD2 Logic Part Input Voltage V I1 Driver Part Input Voltage V I2 Logic Part Output ...

Page 13

... The STB cycle is defined input pattern. The MAX. value refers to the measured values in the dot checkerboard input pattern. 4. Refers to the current consumption per driver when cascades are connected under the assumption of XGA single-sided mounting (10 units). Switching Characteristics (T = – ...

Page 14

Timing Requirement (T = –10 to +75° Parameter Symbol Clock Pulse Width PW CLK Clock Pulse Low Period PW CLK(H) Clock Pulse High Period PW CLK(L) Data Setup Time t SETUP1 Data Hold Time t HOLD1 Start Pulse ...

Page 15

CLK (L) CLK CLK (H) CLK SETUP2 HOLD2 STHR (1st Dr SETUP1 HOLD1 D 301 INVALID ...

Page 16

... RECOMMENDED MOUNTING CONDITIONS When mounting this product, please make sure that the following recommended conditions are satisfied. For packaging methods and conditions other than those recommended below, please contact NEC sales personnel. Mounting Condition Mounting Method Thermocompression Soldering ACF (Adhesive Conductive Film) Caution To find out the detailed conditions for packaging the ACF part, please contact the ACF manufacturing company ...

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... Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance ...

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