HT68F04 Holtek Semiconductor, HT68F04 Datasheet - Page 86

• Manufacturer Part Number: HT68F04
• Description: Small Package Enhanced Flash Type 8-Bit MCU
• Manufacturer: Holtek Semiconductor

Timer/Counter Mode
To select this mode, bits TnAM1, TnAM0 and TnBM1,
TnBM0 in the TMnC1 and TMnC2 register should all be
set high. The Timer/Counter Mode operates in an identi-
cal way to the Compare Match Output Mode generating
the same interrupt flags. The exception is that in the
Timer/Counter Mode the TM output pin is not used.
Therefore the above description and Timing Diagrams
for the Compare Match Output Mode can be used to un-
derstand its function. As the TM output pin is not used in
this mode, the pin can be used as a normal I/O pin or
other pin-shared function.
PWM Output Mode
To select this mode, the required bit pairs, TnAM1,
TnAM0 and TnBM1, TnBM0 should be set to 10 respec-
tively and also the TnAIO1, TnAIO0 and TnBIO1,
TnBIO0 bits should be set to 10 respectively. The PWM
function within the TM is useful for applications which re-
quire functions such as motor control, heating control, il-
lumination control etc. By providing a signal of fixed
frequency but of varying duty cycle on the TM output pin,
a square wave AC waveform can be generated with
varying equivalent DC RMS values.
As both the period and duty cycle of the PWM waveform
can be controlled, the choice of generated waveform is
extremely flexible. In the PWM mode, the TnCCLR bit is
used to determine in which way the PWM period is con-
trolled. With the TnCCLR bit set high, the PWM period
·
·
·
·
Rev. 1.00
ETM, PWM Mode, Edge-aligned Mode, TnCCLR=0
ETM, PWM Mode, Edge-aligned Mode, TnCCLR=1
ETM, PWM Mode, Center-aligned Mode, TnCCLR=0
ETM, PWM Mode, Center-aligned Mode, TnCCLR=1
Period
A Duty
B Duty
CCRA
Period
B Duty
Period
A Duty
B Duty
CCRA
Period
B Duty
CCRP
CCRP
001b
001b
128
256
1
1
1
2
010b
010b
256
512
2
2
2
4
011b
011b
384
768
3
3
3
6
HT66F03/HT66F04/HT68F03/HT68F04
100b
100b
1024
1022
86
512
511
511
511
(CCRA´2)-1
(CCRB´2)-1
(CCRB´2)-1
can be finely controlled using the CCRA registers. In this
case the CCRB registers are used to set the PWM duty
value (for TPnB output pin). The CCRP bits are not used
and TPnA output pin is not used. The PWM output can
only be generated on the TPnB output pin. With the
TnCCLR bit cleared to zero, the PWM period is set using
one of the eight values of the three CCRP bits, in multi-
ples of 128. Now both CCRA and CCRB registers can be
used to setup different duty cycle values to provide dual
PWM outputs on their relative TPnA and TPnB pins.
The TnPWM1 and TnPWM0 bits determine the PWM
alignment type, which can be either edge or centre type.
In edge alignment, the leading edge of the PWM signals
will all be generated concurrently when the counter is re-
set to zero. With all power currents switching on at the
same time, this may give rise to problems in higher
power applications. In centre alignment the centre of the
PWM active signals will occur sequentially, thus reduc-
ing the level of simultaneous power switching currents.
Interrupt flags, one for each of the CCRA, CCRB and
CCRP, will be generated when a compare match occurs
from either the Comparator A, Comparator B or Com-
parator P. The TnAOC and TnBOC bits in the TMnC1 and
TMnC2 register are used to select the required polarity of
the PWM waveform while the two TnAIO1, TnAIO0 and
TnBIO1, TnBIO0 bits pairs are used to enable the PWM
output or to force the TM output pin to a fixed high or low
level. The TnAPOL and TnBPOL bit are used to reverse
the polarity of the PWM output waveform.
CCRA
CCRB
CCRB
101b
101b
1280
1024
640
512
512
512
110b
1021
1021
110b
1536
1021
2042
768
111b
1022
1022
111b
1792
1022
2044
896
April 16, 2010
www.DataSheet4U.com
000b
000b
1024
1023
1023
2046
1023
2046