HT68F04 Holtek Semiconductor, HT68F04 Datasheet - Page 69

• Manufacturer Part Number: HT68F04
• Description: Small Package Enhanced Flash Type 8-Bit MCU
• Manufacturer: Holtek Semiconductor

Standard Type TM Operating Modes
The Standard Type TM can operate in one of five oper-
ating modes, Compare Match Output Mode, PWM Out-
put Mode, Single Pulse Output Mode, Capture Input
Mode or Timer/Counter Mode. The operating mode is
selected using the TnM1 and TnM0 bits in the TMnC1
register.
Compare Output Mode
To select this mode, bits TnM1 and TnM0 in the TMnC1
register, should be set to 00 respectively. In this mode
once the counter is enabled and running it can be
cleared by three methods. These are a counter over-
flow, a compare match from Comparator A and a com-
pare match from Comparator P. When the TnCCLR bit is
low, there are two ways in which the counter can be
cleared. One is when a compare match from Compara-
tor P, the other is when the CCRP bits are all zero which
allows the counter to overflow. Here both TnAF and
TnPF interrupt request flags for Comparator A and Com-
parator P respectively, will both be generated.
If the TnCCLR bit in the TMnC1 register is high then the
counter will be cleared when a compare match occurs
Note:
Rev. 1.00
1. With TnCCLR = 0 the Comparator P match will clear the counter
2. TM output pin controlled only by TnAF flag
3. Output pin reset to initial state by TnON bit rising edge
Compare Match Output Mode - TnCCLR = 0
HT66F03/HT66F04/HT68F03/HT68F04
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from Comparator A. However, here only the TnAF inter-
rupt request flag will be generated even if the value of
the CCRP bits is less than that of the CCRA registers.
Therefore when TnCCLR is high no TnPF interrupt re-
quest flag will be generated. In the Compare Match Out-
put Mode, the CCRA can not be set to ²0².
As the name of the mode suggests, after a comparison
is made, the TM output pin, will change state. The TM
output pin condition however only changes state when
an TnAF interrupt request flag is generated after a com-
pare match occurs from Comparator A. The TnPF inter-
rupt request flag, generated from a compare match
occurs from Comparator P, will have no effect on the TM
output pin. The way in which the TM output pin changes
state are determined by the condition of the TnIO1 and
TnIO0 bits in the TMnC1 register. The TM output pin can
be selected using the TnIO1 and TnIO0 bits to go high,
to go low or to toggle from its present condition when a
compare match occurs from Comparator A. The initial
condition of the TM output pin, which is setup after the
TnON bit changes from low to high, is setup using the
TnOC bit. Note that if the TnIO1 and TnIO0 bits are zero
then no pin change will take place.
April 16, 2010
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