HT68F04 Holtek Semiconductor, HT68F04 Datasheet - Page 120

• Manufacturer Part Number: HT68F04
• Description: Small Package Enhanced Flash Type 8-Bit MCU
• Manufacturer: Holtek Semiconductor

Power Down Mode and Wake-up
Entering the IDLE or SLEEP Mode
There is only one way for the device to enter the SLEEP
or IDLE Mode and that is to execute the ²HALT² instruc-
tion in the application program. When this instruction is
executed, the following will occur:
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Standby Current Considerations
As the main reason for entering the SLEEP or IDLE
Mode is to keep the current consumption of the device
to as low a value as possible, perhaps only in the order
of several micro-amps, there are other considerations
which must also be taken into account by the circuit de-
signer if the power consumption is to be minimised.
Special attention must be made to the I/O pins on the
device. All high-impedance input pins must be con-
nected to either a fixed high or low level as any floating
input pins could create internal oscillations and result in
increased current consumption. This also applies to de-
vices which have different package types, as there may
be unbonbed pins. These must either be setup as out-
puts or if setup as inputs must have pull-high resistors
connected. Care must also be taken with the loads,
which are connected to I/O pins, which are setup as out-
puts. These should be placed in a condition in which
minimum current is drawn or connected only to external
circuits that do not draw current, such as other CMOS
inputs. Also note that additional standby current will also
be required if the configuration options have enabled
the LIRC oscillator.
Rev. 1.00
The system clock will be stopped and the application
program will stop at the ²HALT² instruction.
The Data Memory contents and registers will maintain
their present condition.
The WDT will be cleared and resume counting if the
WDT clock source is selected to come from the f
clock source and the WDT is enabled. The WDT will
stop if its clock source originates from the system clock.
The I/O ports will maintain their present condition.
In the status register, the Power Down flag, PDF, will be
set and the Watchdog time-out flag, TO, will be cleared.
SUB
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HT66F03/HT66F04/HT68F03/HT68F04
Wake-up
After the system enters the SLEEP or IDLE Mode, it can
be woken up from one of various sources listed as follows:
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If the system is woken up by an external reset, the de-
vice will experience a full system reset, however, if the
device is woken up by a WDT overflow, a Watchdog
Timer reset will be initiated. Although both of these
wake-up methods will initiate a reset operation, the ac-
tual source of the wake-up can be determined by exam-
ining the TO and PDF flags. The PDF flag is cleared by a
system power-up or executing the clear Watchdog
Timer instructions and is set when executing the ²HALT²
instruction. The TO flag is set if a WDT time-out occurs,
and causes a wake-up that only resets the Program
Counter and Stack Pointer, the other flags remain in
their original status.
Each pin on Port A can be setup using the PAWU regis-
ter to permit a negative transition on the pin to wake-up
the system. When a Port A pin wake-up occurs, the pro-
gram will resume execution at the instruction following
the ²HALT² instruction.
If the system is woken up by an interrupt, then two possi-
ble situations may occur. The first is where the related
interrupt is disabled or the interrupt is enabled but the
stack is full, in which case the program will resume exe-
cution at the instruction following the ²HALT² instruction.
In this situation, the interrupt which woke-up the device
will not be immediately serviced, but will rather be ser-
viced later when the related interrupt is finally enabled or
when a stack level becomes free. The other situation is
where the related interrupt is enabled and the stack is
not full, in which case the regular interrupt response
takes place. If an interrupt request flag is set high before
entering the SLEEP or IDLE Mode, the wake-up func-
tion of the related interrupt will be disabled.
An external reset
An external falling edge on Port A
A system interrupt
A WDT overflow
April 16, 2010
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