IDT71V432S Integrated Device Technology, IDT71V432S Datasheet - Page 7

• Manufacturer Part Number: IDT71V432S
• Description: 32k X 32 Pipelined Burst Sram
• Manufacturer: Integrated Device Technology

Synchronous Write Function Truth Table
NOTES:
1. L = V
2. Multiple bytes may be selected during the same cycle.
Asynchronous Truth Table
NOTES:
1. L = V
2. Synchronous function pins must be biased appropriately to satisfy operation requirements.
Interleaved Burst Sequence Table (LBO=V
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state.
Linear Burst Sequence Table (LBO=V
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state.
Read
Read
Write
Deselected
Sleep
First Address
Second Address
Fourth Address
First Address
Second Address
Fourth Address
Read
Read
Write all Bytes
Write all Bytes
Write Byte 1
Write Byte 2
Write Byte 3
Write Byte 4
Third Address
Third Address
IDT71V432, 32K x 32 CacheRAM
3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect
IL
IL
, H = V
, H = V
Operation
Operation
(2)
(2)
(2)
(2)
(1)
(1)
IH
IH
, X = Don’t Care.
, X = Don’t Care.
(2)
Sequence 1
Sequence 1
A1
A1
0
0
0
0
1
1
1
1
GW
OE
H
H
H
H
H
H
H
H
X
X
X
L
L
A0
A0
0
0
0
0
1
1
1
1
ZZ
H
L
L
L
L
(1)
BWE
H
X
L
L
L
L
L
L
Sequence 2
Sequence 2
A1
A1
0
0
1
1
0
0
1
1
6.42
7
A0
A0
0
0
0
0
1
1
1
1
High-Z — Data In (I/O
SS
BW
X
H
X
H
H
H
)
L
L
Data Out (I/O
1
(1)
I/O Status
DD
High-Z
High-Z
High-Z
)
0
- I/O
Commercial and Industrial Temperature Ranges
0
Sequence 3
Sequence 3
BW
A1
A1
- I/O
0
0
0
0
X
X
31
1
1
1
1
H
H
H
H
L
L
)
2
31
)
A0
A0
0
0
0
0
1
1
1
1
BW
X
X
H
H
H
H
L
L
3
Sequence 4
Sequence 4
A1
A1
0
0
0
0
1
1
1
1
Standby
Power
Active
Active
Active
Sleep
A0
A0
0
0
0
0
BW
1
1
1
1
X
X
H
H
H
H
L
L
4
3104 tbl 10
3104 tbl 08
3104 tbl 09
3104 tbl 11