SM55161A Austin Semiconductor, SM55161A Datasheet - Page 39

• Manufacturer Part Number: SM55161A
• Description: 262144 x 16 BIT VRAM MULTIPORT VIDEO RAM
• Manufacturer: Austin Semiconductor

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FIGURE 32: ENHANCED-PAGE-MODE WRITE-CYCLE TIMING
NOTES:
A. Referenced to the first falling edge of CASx\ or the falling edge of WE\, whichever occurs later
B. A read cycle or a read-modify-write cycle can be intermixed with write cycles, observing read and read-modify-write timing
specifications. To ensure page-mode cycle time, TRG\ must remain high throughout the entire page-mode operation if the late write
feature is used. If the early write-cycle timing is used, the state of TRG\ is a don’t care after the minimum period t
edge of RAS\..
TABLE 10: ENHANCED-PAGE-MODE WRITE-CYCLE STATE TABLE
NOTES:
a don’t care during this cycle.
Write operation (nonmasked)
Write operation with nonpersistent write-per-bit
Write operation with persistent write-per-bit
Load-write mask on either the first falling edge of CASx\
or the falling edge of WE\, whichever occurs later.
SMJ55161A
Rev. 1.6 03/05
1. Load-write-mask-register cycle puts the device in the persistent write-per-bit mode. Column address at the falling edge of CASx\ is
Austin Semiconductor, Inc.
CYCLE
1
39
H
L
L
1
L
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
L
2
L
L
L
STATE
H
H
3
L
L
h(TRG)
Write Mask Valid Data
Don't Care
Don't Care
Don't Care Write Mask
Production
SM55161A
from the falling
4
VRAM
Valid Data
Valid Data
5