ISL6269B Intersil Corporation, ISL6269B Datasheet
ISL6269B
Related parts for ISL6269B
ISL6269B Summary of contents
Page 1
... PWM controllers. Unlike a conventional hysteretic converter, the ISL6269B has an error amplifier that provides ±1% voltage regulation at the FB pin. The ISL6269B has a 1.5ms digital soft-start and can be started into a pre-biased output voltage. A resistor divider is used to program the output voltage setpoint. The ISL6269B ...
Page 2
Block Diagram VIN GND PACKAGE BOTTOM VCC V REF EN − OVP + − UVP + + EA EA − FB COMP − ISEN OCP 30Ω PGOOD PWM FREQUENCY CONTROL + − + ...
Page 3
... Typical Application R PGOOD 5V R VCC C C PVCC VCC R COMP C COMP1 C COMP2 R BOTTOM 3 ISL6269B ISL6269B PGOOD VIN PVCC UG VCC BOOT GND PHASE FCCM ISEN EN LG COMP PGND FB FSET VO R TOP HIGH_SIDE C L BOOT OUT C R OUT SEN Q LOW_SIDE R C FSET FSET ...
Page 4
... ERROR AMPLIFIER FB Input Bias Current COMP Source Current COMP Sink Current COMP High Clamp Voltage 4 ISL6269B Thermal Information Thermal Resistance (Typical, Notes 1, 2) θ QFN Package Junction Temperature Range .-55°C to +150°C Operating Temperature Range . . . . . . . . . . . . . . . .-10°C to +100°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Lead Temperature (Soldering, 10s +300° ...
Page 5
... ISEN Short-Circuit Threshold UVP Threshold OVP Rising Threshold OVP Falling Threshold OTP Rising Threshold (Note 3) OTP Hysteresis (Note 3) NOTE: 3. Guaranteed by characterization. 5 ISL6269B = -10°C to +100°C, unless otherwise stated +25°C, VCC = 5V, PVCC = 5V (Continued) A SYMBOL TEST CONDITIONS 0.80V, Source 50µA COMP_LC ...
Page 6
... R Connect at the physical location where the best output voltage regulation is desired. 6 ISL6269B ISEN (Pin 9) The ISEN pin programs the threshold of the OCP overcurrent fault protection. Program the desired OCP threshold with a resistor connected across the ISEN and PHASE pins ...
Page 7
... FIGURE 2. MODULATOR WAVEFORMS DURING LOAD TRANSIENT 7 ISL6269B Power-On Reset The ISL6269B is disabled until the voltage at the VCC pin has increased above the rising power-on reset (POR) V threshold voltage. The controller will become once again 3 disabled when the voltage at the VCC pin decreases below ...
Page 8
... BOOT and PHASE pins. The boot capacitor is charged from a 5V bias supply through a “boot diode” each time the low-side MOSFET turns on, pulling the PHASE pin low. The ISL6269B has an integrated boot diode connected from the PVCC pin to the BOOT pin. t ...
Page 9
... FB and GND pins has fallen below the undervoltage threshold V (EQ. 3) Over-Temperature When the temperature of the ISL6269B increases above the rising threshold temperature T (EQ. 4) state that suspends the PWM , forcing the LG and UG gate-driver outputs low. The status of the PGOOD pin does not change nor does the converter latch-off ...
Page 10
... BOTTOM V V – OUT REF Programming the PWM Switching Frequency The ISL6269B does not use a clock signal to produce PWM. The PWM switching frequency F is programmed by the SW resistor R that is connected from the FSET pin to the FSET GND pin. The approximate PWM switching frequency is ...
Page 11
... A capacitor dissipates heat as a function of RMS current and frequency. Be sure that I 11 ISL6269B shared by a sufficient quantity of paralleled capacitors so that they operate below the maximum rated RMS current at F Take into account that the rated value of a capacitor can fade as much as 50% as the DC voltage across it increases ...
Page 12
... OFF SW ground (GND) terminal for analog and logic signals of the IC. 2 Connect the GND pad of the ISL6269B to the island of (EQ. 17) ground plane under the top layer using several vias, for a robust thermal and electrical conduction path. Connect the input capacitors, the output capacitors, and the source of the lower MOSFETs to the power ground plane ...
Page 13
... Route the connection to the ISEN pin away from the traces and components connected to the FB pin, COMP pin, and FSET pin. 13 ISL6269B LG (Pin 11) The signal going through this trace is both high dv/dt and high di/dt, with high peak charging and discharging current. Route this trace in parallel with the trace from the PGND pin. ...
Page 14
... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 14 ISL6269B L16.4x4 16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220-VGGC ISSUE C) ...