ISL6262 Intersil Corporation, ISL6262 Datasheet
ISL6262
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ISL6262 Summary of contents
Page 1
... While the PSI# is asserted at the medium load in the active mode, the ISL6262 smoothly disables one phase and operates in a one-phase CCM. When the CPU enters deeper sleep mode, the ISL6262 enables diode emulation to maximize the efficiency at the light load ...
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... Pinout PGOOD PSI# PGD_IN RBIAS VR_TT# NTC SOFT OCSET VW COMP FB FB2 www.DataSheet4U.com 2 ISL6262 ISL6262 (7x7 QFN) TOP VIEW GND PAD (BOTTOM BOOT1 35 UGATE1 34 PHASE1 33 PGND1 ...
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... No load, closed loop, active mode 0°C to 100°C, VID = 0.75-1.5V cc_core A ISL6262CRZ VID = 0.5-0.7375V VID = 0.3-0.4875V %Error T = -40°C to 100°C, VID = 0.75-1. cc_core VID = 0.5-0.7375V ISL6262IRZ VID = 0.3-0.4875V 147kΩ RBIAS RBIAS V BOOT V VID = [0000000] CC_CORE (max) V VID = [1100000] CC_CORE (min) VID = [1111111] ...
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... PDHU 5V, Outputs Unloaded CC ISL6262CRZ 5V, Outputs Unloaded PDHU CC ISL6262IRZ -10°C to 100°C PDHL 5V, Outputs Unloaded CC ISL6262CRZ 5V, Outputs Unloaded PDHL CC ISL6262IRZ V = 5V, Forward Bias Current = 2mA DDP V = 16V 4mA OL PGOOD 3.3V OH GOOD MIN TYP MAX UNITS -0 ...
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... A SYMBOL TEST CONDITIONS -10°C to 100°C pgd A CLK_EN# Low to PGOOD High ISL6262CRZ t CLK_EN# Low to PGOOD High pgd ISL6262IRZ O V rising above setpoint > 1ms rising above setpoint > 0.5µs VHS O I(Rbias) = 10µA DROOP rising above OCSET > 120µs Difference between ISEN1 and ISEN2 > 1ms ...
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... ISL6262 Gate Driver Timing Diagram PWM UGATE LGATE t FL Functional Pin Description PGOOD PSI# PGD_IN RBIAS VR_TT# NTC SOFT OCSET VW COMP FB FB2 PGOOD - Power good open-drain output. Will be pulled up externally by a 680Ω resistor to VCCP or 1.9kΩ to 3.3V. PSI# - Low load current indicator input. When asserted low, indicates a reduced load-current condition, and product goes into single phase operation ...
Page 7
... LGATE2 - Lower-side MOSFET gate signal for phase 2. www.DataSheet4U.com PVCC - 5V power supply for gate drivers. 7 ISL6262 LGATE1 - Lower-side MOSFET gate signal for phase 1. PGND1 - The return path of the lower gate driver for phase 1. PHASE1 - The phase node of phase 1. This pin should connect to the source of upper MOSFET ...
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... OC CH1 CH1 CH2 PHASE SEQUENCER PHASE CONTROL P GOOD LOGIC SINGLE PHASE PGOOD LOGIC VO SOFT SINGLE PHASE DACOUT MODE DAC CONTROL FIGURE 1. SIMPLIFIED FUNCTION BLOCK DIAGRAM OF ISL6262 PVCC PVCC DRIVER LOGIC FLT VSOFT VIN MODULATOR OC CH2 Vw Vw SINGLE PHASE VO E/A - VIN VSOFT ...
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... FIGURE 4. ACTIVE MODE EFFICIENCY, 1 PHASE, CCM, PSI# = LOW, VID = 1.15V 100 8. 19. 0.1 I OUT www.DataSheet4U.com FIGURE 6. DEEPER SLEEP MODE EFFICIENCY, 1 PHASE, DCM MODE, VID = 0.7625V 9 ISL6262 300kHz, DCR Sense, 2xIRF7821/2xIRF7832 Per Phase ( (A) = 12. ( ...
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... OUT www.DataSheet4U.com FIGURE 12. 8V-20V INPUT LINE TRANSIENT RESPONSE 240µ ISL6262 0.36µH Filter Inductor and 4 x 330µF Output SP Caps V OUT C = 15nF SOFT FIGURE 9. SOFT-START WAVEFORM SHOWING SLEW RATE = 10A LOAD IMVP-6_PWRGD FIGURE 11. INRUSH CURRENT AT START-UP, V LINE TRANSIENT FIGURE 13 ...
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... V CORE PHASE1 PHASE2 FIGURE 18. 2-CCM TO 1-CCM UPON PSI# ASSERTION WITH www.DataSheet4U.com VID LSB CHANGE, AT DPRSLPVR = 0, DPRSTP LOAD 11 ISL6262 0.36µH Filter Inductor and 4 x 330µF Output SP Caps (Continued) LOAD TRANSIENT LOAD TRANSIENT DROP PHASE IN ACTIVE MODE = 10A VID3 V OUT PHASE1, PHASE2 FIGURE 15 ...
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... V OUT PGOOD IL1, IL2 FIGURE 24. OVERCURRENT PROTECTION www.DataSheet4U.com 12 ISL6262 0.36µH Filter Inductor and 4 x 330µF Output SP Caps (Continued) C4 ENTRY WITH PSI# ASSERTION FIGURE 21. VID3 CHANGE OF 010X000 FROM 1 2A, TRANSITION OF FIGURE 23. C4 ENTRY WITH VID CHANGE OF 011X011 FROM FIGURE 25. 1.7V OVERVOLTAGE PROTECTION SHOWS ...
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... VR_ON IMVP-6_PWRGD REMOTE SENSE FSET C 9 FIGURE 26. ISL6262 BASED TWO-PHASE BUCK CONVERTER WITH INDUCTOR DCR CURRENT SENSING www.DataSheet4U.com 13 ISL6262 +3.3 3V3 VDD PVCC VIN RBIAS NTC VR_TT# UGATE1 SOFT BOOT1 C 6 VIDs PHASE1 ...
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... VR_ON IMVP-6_PWRGD REMOTE SENSE FSET C 9 FIGURE 27. ISL6262 BASED TWO-PHASE BUCK CONVERTER WITH RESISTIVE CURRENT SENSING www.DataSheet4U.com 14 ISL6262 +3.3 3V3 VDD PVCC VIN RBIAS NTC VR_TT# UGATE1 SOFT BOOT1 C 6 VIDs PHASE1 DPRSTP# ...
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... VID inputs per Table 1. The entire VID 3 regulator table is presented in the intel IMVP-6 specification. The ISL6262 will control the no-load output voltage to an accuracy of ±0.5% over the range of 0.75V to 1.5V. TABLE 1. TRUNCATED VID TABLE FOR INTEL IMVP-6 VID6 ...
Page 16
... DPRSTP# as shown in Table 2. At high current levels, the system will operate with both phases fully active, responding rapidly to transients and deliver the maximum power to the load. At reduced load current levels, one of the phases may TABLE 2. CONTROL SIGNAL TRUTH TABLES FOR OPERATION MODES OF ISL6262 DPRSLPVR Intel IMVP-6 0 ...
Page 17
... As load is further reduced, the phase 1 channel switching frequency will decrease, thus maintaining high efficiency. Dynamic Operation Refer to Figure 29, the ISL6262 responds to changes in VID command voltage by slewing to new voltages with a dV/dt set by the SOFT capacitor and by the state of DPRSLPVR. With C voltage will move at ± ...
Page 18
... ISL6262 threshold, the VR_TT# pin is pulled low indicating the need for thermal throttling to the system oversight processor. No other action is taken within the ISL6262 in response to NTC pin voltage. Component Selection and Application Soft-Start and Mode Change Slew Rates The ISL6262 uses 2 slew rates for various modes of operation ...
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... SOFT CPU die is the correct level independent of load current. (EQ. 2) The VSEN and RTN pins of the ISL6262 are connected to Kelvin sense leads at the die of the processor through the processor socket. These signal names are Vcc_sense and value, given in the Vss_sense respectively ...
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... Refer to Figure 26, the resistor connected between the VW and COMP pins of the ISL6262 adjusts the switching window, and therefore adjusts the switching frequency. The R resistor that sets up the switching frequency of the ...
Page 21
... NTC 2 NTC 1 21 ISL6262 Using Equation 5 into Equation 8, the required nominal NTC resistor value can be obtained by: R For some cases, the constant b is not accurate enough to approximate the NTC resistor value, the manufacturer provides the resistor ratio information at different temperature. The nominal NTC resistor value may be ...
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... Static Mode of Operation - Static Droop Using DCR Sensing As previously mentioned, the ISL6262 has an internal differential amplifier which provides for very accurate voltage regulation at the die of the processor. The load line regulation is also accurate for both two-phase and single- phase operation ...
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... ISL6262 Note, we choose to ignore the RO resistors because they do not add significant error. (EQ. 16) These designed values in Rn network are very sensitive to layout and coupling factor of the NTC to the inductor. As only ) (EQ. 17) one NTC is required in this application, this NTC should be ...
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... ISL6262 uses RC filter to sense the average voltage on phase node and forces the average voltage on the phase node to be equal for current balance. Even though the ISL6262 forces the ISEN voltages to be almost equal, the inductor currents will not be exactly equal. Take DCR current (EQ. 25) sensing as example, two errors have to be added to find the total current imbalance ...
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... Fault Protection - Overcurrent Fault Setting As previously described, the overcurrent protection of the ISL6262 is related to the droop voltage. Previously we have calculated that the droop voltage = ILoad * Rdroop, where Rdroop is the load line slope specified as 0.0021 (V/A) in the Intel IMVP-6 specification. Knowing this relationship, the overcurrent protection threshold can be set voltage droop level ...
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... OC + INTERNAL TO ISL6262 + VDIFF RTN FIGURE 36. EQUIVALENT MODEL FOR DROOP AND DIE SENSING USING DISCRETE RESISTOR SENSING www.DataSheet4U.com 26 ISL6262 Voc - OCSET Roc VSUM VSUM + DROOP DFB - DROOP + VO' VSEN VO' RS -------- RS = EQV 2 Rsense × Vrsense I --------------------- - = EQV OUT -------- - = EQV 2 May 15, 2006 ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 27 ISL6262 L48.7x7 48 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220VKKD-2 ISSUE C) ...