AD1939 Analog Devices, AD1939 Datasheet
AD1939
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AD1939 Summary of contents
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... Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. AD1935/AD1936/AD1937/AD1938/AD1939 2 S and TDM Modes Digital Audio ...
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... AD1935/AD1936/AD1937/AD1938/AD1939 AD193X—SPECIFICATIONS Test Conditions, Unless Otherwise Noted. Performance of all channels is identical (exclusive of the Inter-channel Gain Mismatch and Inter-channel Phase Deviation specifications). Parameter Supply Voltages (AVDD, DVDD) Case Temperature Master Clock Input Signal Input Sample Rate Measurement Bandwidth Word Width Load Capacitance (Digital Output) ...
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... OL OL Input Capacitance Power Supplies Parameter Supplies Dissipation Power Supply Rejection Ratio AD1935/AD1936/AD1937/AD1938/AD1939 Interchannel Gain Mismatch Offset Error, Single-ended version Offset Error, Differential version Gain Drift Interchannel Isolation Interchannel Phase Deviation Volume Control Step Volume Control Range De-emphasis Gain Error ...
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... AD1935/AD1936/AD1937/AD1938/AD1939 Temperature Range Parameter Specifications Guaranteed Functionality Guaranteed Storage Digital Filters Mode ADC All Modes, DECIMATION Typ @ 48 kHz FILTER 48 kHz Mode, Typ @ 48 kHz DAC 96 kHz Mode, INTERPOLATION Typ @ 96 kHz FILTER 192 kHz Mode, Typ @ 192 kHz Timing Specifications Parameter ...
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... ADC SERIAL PORT t t Master Mode AUXILIARY INTERFACE AD1935/AD1936/AD1937/AD1938/AD1939 Comments CCLK Frequency CCLK CDATA Setup To CCLK Rising CDS CDATA Hold From CCLK Rising CDH CLATCH Setup To CCLK Rising CLS CLATCH Hold From CCLK Falling CLH CLATCH High ...
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... AD1935/AD1936/AD1937/AD1938/AD1939 ABSOLUTE MAXIMUM RATINGS Parameter Min Analog (AVDD) –0.3 Digital (DVDD) –0.3 Input Current (Except Supply Pins) Analog Input Voltage (Signal Pins) –0.3 Digital Input Voltage (Signal Pins) –0.3 Case Temperature (Operating) –40 Table 9 Stresses above those listed under the Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only ...
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... Preliminary Technical Data Figure 2. ADC Passband Filter Response, 48 kHz Figure 4. DAC Passband Filter Response, 48 kHz Figure 6. DAC Passband Filter Response, 96 kHz AD1935/AD1936/AD1937/AD1938/AD1939 Figure 3. ADC Stopband Filter Response, 48 kHz Figure 5. DAC Stopband Filter Response, 48 kHz Figure 7. DAC Stopband Filter Response, 96 kHz Rev. PrI | Page ...
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... AD1935/AD1936/AD1937/AD1938/AD1939 Figure 8. DAC Passband Filter Response, 192 kHz Preliminary Technical Data Figure 9. DAC Stopband Filter Response, 192 kHz Rev. PrI | Page ...
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... Note that the use of op amps with low slew AD1935/AD1936/AD1937/AD1938/AD1939 rate or low bandwidth may cause high frequency noise and tones to fold down into the audio band; care should be exercised in selecting these components ...
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... Master 0 The SPI control port of the AD1938 and AD1939 is a 4-wire serial control port. The format is similar to the Motorola SPI format except the input data-word is 24 bits wide. The serial bit clock and latch may be completely asynchronous to the sample rate of the ADCs and DACs ...
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... It is important that the analog supply be as clean as possible. The AD1935 (64-pin single-ended version), and the AD1939 and AD1937 (64-pin differential versions) include a 3.3V regulator driver which requires only an external pass transistor and bypass capacitors to make ...
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... AD1935/AD1936/AD1937/AD1938/AD1939 Serial Data Ports—Data Format The eight DAC channels output or accept a common serial bit clock and left-right framing clock to clock in the serial data. The four ADC channels output or accept a common serial bit clock and left- right framing clock to clock out the data. The clock signals are all synchronous with the sample rate ...
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... MODE t ABH ABCLK t ABL t ALS ALRCLK t ABDD ASDATA LEFT-JUSTIFIED MODE ASDATA 2 I S-JUSTIFIED MODE ASDATA RIGHT-JUSTIFIED MODE AD1935/AD1936/AD1937/AD1938/AD1939 t DBP MSB-1 t DDS MSB t DDH t DDS Figure 14. DAC Serial Timing t ABP MSB MSB-1 t ABDD MSB t ABDD Figure 15. ADC Serial Timing Rev. PrI | Page ...
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... AD1935/AD1936/AD1937/AD1938/AD1939 LRCLK LRCLK BCLK BCLK DATA DATA LRCLK LRCLK BCLK BCLK DATA DATA FSTDM BCLK TDM MSB TDM ASDATA1 1ST CH TDM (OUT) ADC L1 ASDATA 32 MSB TDM DSDATA1 1ST CH TDM (IN) DSDATA1 DAC L1 32 AUX LRCLK (FROM AUX ADC 1) AUX BCLK (FROM AUX ADC 1) ...
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... LRCLK BCLK AUX ADC 2 DATA MCLK Figure 19. Example of AUX Mode Connection to SHARC (AD193X as TDM Master/AUX Master shown) AD1935/AD1936/AD1937/AD1938/AD1939 TDM Modes ADC TDM Data Out ADC TDM Data In DAC TDM Data In DAC TDM Data Out DAC TDM Data In 2 (dual-line mode) DAC TDM Data Out 2 (dual-line mode) ...
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... AD1935/AD1936/AD1937/AD1938/AD1939 PIN FUNCTION DESCRIPTIONS 48-Lead LQFP Plastic Package – AD1936, AD1938 Pin No. In/Out Mnemonic Description 1 I AGND Analog Ground MCLKI/XI Master Clock Input/ Crystal Oscillator Input MCLK/XO Master Clock Output/ Crystal Oscillator Output AGND Analog Ground AVDD Analog Power Supply ...
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... Preliminary Technical Data 64-Lead LQFP Plastic Package – AD1937, AD1939 Pin No. In/Out Mnemonic Description 1 I AGND Analog Ground MCLKI/XI Master Clock Input/ Crystal Oscillator Input MCLK/XO Master Clock Output/ Crystal Oscillator Output AGND Analog Ground AVDD Analog Power Supply. Connect to analog 3.3 V supply. ...
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... DVDD Digital Power Supply. Connect to digital 3.3 V supply DGND Digital Ground CCLK Control Clock Input (SPI) CLATCH 35 I Latch Input for Control Data (SPI) Table 14. Pin Function Description—64-Lead LQFP (AD1937, AD1939) Rev. PrI | Page Preliminary Technical Data ...
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... ADC2 Right Negative Input PLL Loop Filter, Return to AVDD AVDD Analog Power Supply. Connect to analog 3.3 V supply Connect Connect. PIN CONFIGURATION AD1935/AD1936/AD1937/AD1938/AD1939 Table 15. Pin Function Description—64-Lead LQFP (AD1935 AGND 1 MCLKI/XI 2 MCLKO/XO 3 AGND 4 AD193X ...
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... Scale) 9 Differential OL4P 10 Output OL4N 11 12 Preliminary Figure 21. Differential Output 64-Lead LQFP (AD1937, AD1939 OL3 6 AD193X NC 7 TOP VIEW OR3 8 (Not to Scale) ...
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... Preliminary Technical Data APPLICATION CIRCUITS Figure 24. Typical DAC Output Filter Circuit (Single-ended, Non-inverting) AD1935/AD1936/AD1937/AD1938/AD1939 Figure 23. Typical ADC Input Filter Circuit Figure 25. Typical DAC Output Filter Circuit (Single-ended, Inverting) Figure 26. Typical DAC Output Filter Circuit (Differential) Rev. PrI | Page ...
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... AD1935/AD1936/AD1937/AD1938/AD1939 Figure 27. Recommended Loop Filters for LRCLK or MCLK PLL reference. Figure 28. Recommended 3.3V Regulator Circuit (64-lead versions) Rev. PrI | Page Preliminary Technical Data ...
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... DAC 1L Vol Control 7 DAC 1R Vol Control 8 DAC 2L Vol Control 9 DAC 2R Vol Control 10 DAC 3L Vol Control 11 DAC 3R Vol Control 12 DAC 4L Vol Control 13 DAC 4R Vol Control 14 ADC Control 0 15 ADC Control 1 16 ADC Control 2 AD1935/AD1936/AD1937/AD1938/AD1939 Register Address Data 15:8 7:0 Table 16 Table 17 Rev. PrI | Page ...
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... AD1935/AD1936/AD1937/AD1938/AD1939 PLL AND CLOCK CONTROL REGISTERS PLL and Clock control 0 Bit Value Function 0 0 Normal operation 1 Power down 2:1 00 INPUT 256 (x 44.1 or 48kHz) 01 INPUT 384 (x 44.1 or 48kHz) 10 INPUT 512 (x 44.1 or 48kHz) 11 INPUT 768 (x 44.1 or 48kHz) 4:3 00 XTAL Oscillator Enabled 01 256xfs VCO Output 10 512xfs VCO Output ...
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... Slave 1 Master 6 0 DBCLK pin 1 Internally generated 7 0 Normal 1 Inverted AD1935/AD1936/AD1937/AD1938/AD1939 Description Power Down Sample Rate SDATA Delay (BCLK periods) Serial Format Table 20 Description BCLK Active Edge (TDM In) BCLKs Per Frame LRCLK Polarity LRCLK Master/Slave BCLK Master/Slave BCLK Source BCLK Polarity Table 21 Rev ...
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... AD1935/AD1936/AD1937/AD1938/AD1939 DAC control 2 Bit Value Function 0 0 Unmute 1 Mute 2:1 00 Flat 01 48 kHz Curve 10 44.1 kHz Curve 11 32 kHz Curve 4 Reserved Non-inverted 1 Inverted 7:6 00 Reserved DAC Individual Channel Mutes Bit Value Function 0 0 Unmute 1 Mute 1 0 Unmute 1 Mute 2 0 Unmute ...
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... TDM (Daisy Chain) 10 ADC Aux mode (ADC, DAC TDM coupled) 11 Reserved 7 0 Latch in mid cycle (normal) 1 Latch in at end of cycle (pipeline) AD1935/AD1936/AD1937/AD1938/AD1939 Description Power Down Highpass Filter ADC 1L mute ADC 1R mute ADC 2L mute ADC 2R mute Output Sample Rate Table 25 Description Word width ...
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... AD1935/AD1936/AD1937/AD1938/AD1939 ADC control 2 Bit Value Function 0 0 50/50 (allows 32/24/20/16 BCLK/channel) 1 Pulse (32 BCLK/channel Drive out on falling edge (DEF) 1 Drive out on rising edge 2 0 Left Low 1 Left High 3 0 Slave 1 Master 5 128 10 256 11 512 6 0 Slave 1 Master 7 0 ABCLK pin 1 Internally generated ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. AD1935/AD1936/AD1937/AD1938/AD1939 0.75 1.60 0.60 MAX 0 ...
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... LQFP, SE out, SPI control 64-Lead LQFP, Diff out, SPI control 64-Lead LQFP, Diff out, SPI control AD1935 Evaluation Board AD1936 Evaluation Board AD1937 Evaluation Board AD1938 Evaluation Board AD1939 Evaluation Board Table 28. Ordering Guide Rev. PrI | Page Package Option ST-64 ST-64 on 13” Reels ST-48 ST-48 on 13” ...