AD1821 Analog Devices, AD1821 Datasheet - Page 19

• Manufacturer Part Number: AD1821
• Manufacturer: Analog Devices

PNPR
PDN
The SDFS pin is used for the serial interface frame synchronization. New frames are marked by a one SCLK duration HI pulse,
driven out on SDFS, one serial clock period before the frame begins. Upon initializing, there are exactly 12 time slots per frame and
16 bits per time slot. The frame rate is 57,291 and 2/3 Hz (11 MHz SCLK /(16 bits 12 slots). The frame rate can also be changed
from the default value by reprogramming the rate in registers. The frame rate can run at the default rate or be programmed to match
the modem sample rate, ADC capture rate, DAC playback rate, music sample rate, I
the frame rate is not equivalent to the sample rate, Valid Out, Request In and Valid In bits are used to control the sample data flow.
When the frame rate is equivalent to the sample rate, Valid and Request bits can be ignored.
REV. 0
SDI OR
SCLK
SDFS
SDO
SDI OR SDO
SCLK
SDFS
Plug and Play Reset flag. This bit is set by an AD1821 reset (RESETB pin asserted LOW) or by a Plug and Play
reset command. This bit is cleared by the assertion of the FCLR bit in the control word. While this bit is set, all
attempts to write an SS indirect register via the DSP port will be ignored and fail. This is to ensure that Plug and
Play resets are immediately applied to the application running on the DSP, without requiring them to continuously poll
the Plug and Play reset status bit. During the frame in which this bit is cleared (by asserting FCLR), an attempt to
write an SS indirect register will succeed. If the FCLR bit is continuously asserted, writes to indirect registers via
the DSP port will always be enabled. A Plug and Play reset command will set this PNPR bit HIGH during at least
one frame.
Power-Down flag. This bit is set by an AD1821 reset (RESETB pin asserted LOW), or by an AD1821 power-
down. Before an AD1821 power-down sequence shuts down the DSP port, at least one frame will be sent with this
bit set. This bit can be cleared by the assertion of the FCLR (DSP port status clear) bit in the control word, pro-
viding the AD1821 is no longer in power-down.
15 14 13
SLOT 0
SAMPLE PERIOD N
Figure 13. DSP Serial Interface (User Programmed Frame Rate)
15 14 13
Figure 12. DSP Serial Interface (Default Frame Rate)
3
SLOT 0
SLOT 15
2
SAMPLE PERIOD N
1
0
3
SLOT 15
2
1
0
15 14 13
15 14 13
SLOT 0
–19–
SLOT 0
SAMPLE PERIOD N + 1
SAMPLE PERIOD N + 1
3
SLOT 15
3
2
SLOT 15
2
1
1
2
S(1) sample rate or I
0
0
15 14 13
SLOT 0
SAMPLE PERIOD N + 2
15 14 13
SLOT 0
SAMPLE PERIOD N + 2
3
2
S(0) sample rate. When
SLOT 15
2
1
0
AD1821
3
SLOT 15
2
1
0