ADS1255IDB Burr-Brown Corporation, ADS1255IDB Datasheet - Page 21
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ADS1255IDB
Manufacturer Part Number
ADS1255IDB
Description
Very Low Noise/ 24-Bit Analog-to-Digital Converter
Manufacturer
Burr-Brown Corporation
Datasheet
1.ADS1255IDB.pdf
(39 pages)
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Settling Time Using the Input Multiplexer
The most efficient way to cycle through the inputs is to
change the multiplexer setting (using a WREG command
to the multiplexer register MUX) immediately after DRDY
goes low. Then, after changing the multiplexer, restart the
conversion process by issuing the SYNC and WAKEUP
commands, and retrieve the data with the RDATA
command. Changing the multiplexer before reading the
data allows the ADS1256 to start measuring the new input
channel sooner. Figure 19 demonstrates efficient input
cycling. There is no need to ignore or discard data while
cycling through the channels of the input multiplexer
because the ADS1256 fully settles before DRDY goes low,
indicating data is ready.
Step 1: When DRDY goes low, indicating that data is ready
for retrieval, update the multiplexer register MUX using the
WREG command. For example, setting MUX to 23h gives
AIN
Step 2: Restart the conversion process by issuing a SYNC
command immediately followed by a WAKEUP command.
Make sure to follow timing specification t
commands.
Step 3: Read the data from the previous conversion using
the RDATA command.
Step 4: When DRDY goes low again, repeat the cycle by
first updating the multiplexer register, then reading the
previous data.
Register
DRDY
DO UT
P
MUX
DIN
www.ti.com
= AIN2, AIN
AIN
P
= AIN0, AIN
01h
WREG 23h
to MUX reg
N
N
= AIN 1
= AIN3.
SYNC
Figure 19. Cycling the ADS1256 Input Multiplexer
WAKEUP
AIN P = AIN2, AIN
23h
RDATA
11
N
= AIN3
t
18
between
MUX = 01h
Data from
Table 14 gives the effective overall throughput (1/t
cycling the input multiplexer. The values for throughput
(1/t
WREG command and f
NOTE: f CLKIN = 7.68MHz.
19
WREG 45h
to MUX reg
Table 14. Multiplexer Cycling Throughput
) assume the multiplexer was changed with a 3-byte
DATA RATE
30,000
15,000
(SPS)
7500
3750
2000
1000
500
100
2.5
60
50
30
25
15
10
5
SYNC
SBAS288D − JUNE 2003 − REVISED AUGUST 2004
WAKEUP
AIN
SCLK
P
= AIN4, AIN
t
CYCLING THROUGHPUT (1/t 19 )
19
= f
45h
CLKIN
RDATA
N
= AIN5
/4.
4374
3817
3043
2165
1438
(Hz)
837
456
2.5
98
59
50
30
25
15
10
5
MU X = 2 3h
D ata from
ADS1255
ADS1256
19
) when
21