MAX199 Maxim, MAX199 Datasheet - Page 11

• Manufacturer Part Number: MAX199
• Description: Multi-Range (4V / 2V / +4V / +2V) / +5V Supply / 12-Bit DAS with 8+4 Bus Interface
• Manufacturer: Maxim

Figure 6. Conversion Timing Using External Acquisition Mode
A standard interrupt signal, INT, is provided to allow the
device to flag the µP when the conversion has ended
and a valid result is available. INT goes low when the
conversion is complete and the output data is ready
(Figures 5 and 6). It returns high on the first read cycle
or if a new control byte is written.
The MAX199 operates with either an internal or an
external clock. Control bits (D6, D7) select either inter-
nal or external clock mode. Once the desired clock
mode is selected, changing these bits to program
power-down will not affect the clock mode. In each
mode, internal or external acquisition can be used. At
power-up, the MAX199 defaults to external clock mode.
Select internal clock mode to free the µP from the
burden of running the SAR conversion clock. To select
this mode, write the control byte with D7 = 0 and D6 = 1.
A 100pF capacitor between the CLK pin and ground
sets this frequency to 1.56MHz nominal. Figure 7
+5V Supply, 12-Bit DAS with 8+4 Bus Interface
CS
D7–D0
INT
HBEN
DOUT
WR
RD
t
CSWS
______________________________________________________________________________________
How to Read a Conversion
t
DS
ACQMOD = "1"
t
t
CS
WR
CONTROL
BYTE
HIGH-Z
Internal Clock Mode
Multi-Range (±4V, ±2V, +4V, +2V),
t
t
CSHW
DH
Clock Modes
t
ACQI
ACQMOD = "0"
CONTROL
BYTE
t
CONV
shows a linear relationship between the internal clock
period and the value of the external capacitor used.
Figure 7. Internal Clock Period vs. Clock Pin Capacitance
t
D0
1500
1000
2000
500
0
0
t
CSRS
50
t
HIGH / LOW
BYTE VALID
INT1
CLOCK PIN CAPACITANCE (pF)
100 150 200
t
D01
HIGH / LOW
BYTE VALID
250
300
350
t
CSRH
t
HIGH-Z
TR
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