MAX1718 Maxim, MAX1718 Datasheet - Page 26

• Manufacturer Part Number: MAX1718
• Description: Notebook CPU Step-Down Controller for Intel Mobile Voltage Positioning IMVP-II
• Manufacturer: Maxim

Notebook CPU Step-Down Controller for Intel
Mobile Voltage Positioning (IMVP - II)
age rating rather than by capacitance value (this is true
of tantalums, OS-CONs, and other electrolytics).
When using low-capacity filter capacitors such as
ceramic or polymer types, capacitor size is usually
determined by the capacity needed to prevent V
and V
sients. Generally, once enough capacitance is added
to meet the overshoot requirement, undershoot at the
rising load edge is no longer a problem (see the V
equation in the Design Procedure section). The amount
of overshoot due to stored inductor energy can be cal-
culated as:
where I
Stability is determined by the value of the ESR zero rela-
tive to the switching frequency. The voltage-positioned
circuit in this data sheet has the ESR zero frequency low-
ered due to the external resistor in series with the output
capacitor ESR, guaranteeing stability. For a voltage-posi-
tioned circuit, the minimum ESR requirement of the output
capacitor is reduced by the voltage-positioning resistor
value.
The boundary condition of instability is given by the fol-
lowing equation:
where R
positioning resistor (Figure 1, R8). For good phase mar-
gin, it is recommended to increase the equivalent RC
time constant by a factor of two. The standard applica-
tion circuit (Figure 1) operating at 300kHz with C
1320µF, R
meets this requirement. In some applications, the C
and R
even if R
The easiest method for checking stability is to apply a
very fast zero-to-max load transient and carefully
observe the output voltage ripple envelope for over-
shoot and ringing. Don’t allow more than one cycle of
ringing after the initial step-response under/overshoot.
The input capacitor must meet the ripple current
requirement (I
defined by the following equation:
26
______________________________________________________________________________________
DROOP
SOAR
PEAK
(R
ESR
DROOP
ESR
ESR
from causing problems during load tran-
is the peak inductor current.
= 0.
values are sufficient to guarantee stability
+ R
RMS
= 2.5mΩ, and R
V
is the effective value of the voltage-
SOAR
DROOP
) imposed by the switching currents
Output Capacitor Stability
Input Capacitor Selection
≈
)
2
✕
L I
×
C
×
C
OUT
PEAK
×
V
DROOP
OUT
≥ 1 / (2
2
Considerations
= 5mΩ easily
✕
f
SW
)
OUT
SAG
SAG
OUT
=
For most applications, nontantalum chemistries (ceramic
or OS-CON) are preferred due to their resistance to
inrush surge currents typical of systems with a switch
or a connector in series with the battery. If the
MAX1718 is operated as the second stage of a two-
stage power-conversion system, tantalum input capaci-
tors are acceptable. In either configuration, choose an
input capacitor that exhibits less than +10°C tempera-
ture rise at the RMS input current for optimal circuit
longevity.
Most of the following MOSFET guidelines focus on the
challenge of obtaining high load-current capability
(>12A) when using high-voltage (>20V) AC adapters.
Low-current applications usually require less attention.
The high-side MOSFET must be able to dissipate the
resistive losses plus the switching losses at both
V
Ideally, the losses at V
to the losses at V
If the losses at V
losses at V
Conversely, if the losses at V
higher than the losses at V
the size of Q1. If V
the minimum power dissipation occurs where the resis-
tive losses equal the switching losses.
Choose a low-side MOSFET (Q2) that has the lowest
possible R
(i.e., two or more SO-8s, DPAKs or D
sonably priced. Ensure that the MAX1718 DL gate dri-
ver can drive Q2; in other words, check that the dv/dt
caused by Q1 turning on does not pull up the Q2 gate
due to drain-to-gate capacitance, causing cross-con-
duction problems. Switching losses aren’t an issue for
the low-side MOSFET since it’s a zero-voltage switched
device when used in the buck topology.
The high-side MOSFET power dissipation due to resis-
tance is:
Generally, a small high-side MOSFET is desired to
reduce switching losses at high input voltages.
However, the R
IN(MIN)
PD Q
(
and V
I
DS(ON)
RMS
IN(MAX)
1
Re
IN(MAX)
sistive
DS(ON)
=
IN(MIN)
IN(MAX)
, comes in a moderate-sized package
I
LOAD
, consider increasing the size of Q1.
IN
MOSFET Power Dissipation
)
does not vary over a wide range,
Power MOSFET Selection
. Calculate both of these sums.
=
IN(MIN)
required to stay within package
are significantly higher than the
, with lower losses in between.
V
V
V
OUT
OUT
IN
IN(MIN)
should be roughly equal
IN(MAX)
×
(
V
V
I
IN
LOAD
IN
, consider reducing
−
2
PAKs), and is rea-
V
2
OUT
are significantly
×
R
)
DS ON
(
)