AD9516-3 Analog Devices, AD9516-3 Datasheet - Page 74
![no-image](/images/manufacturer_photos/0/0/56/analog_devices_sml.jpg)
AD9516-3
Manufacturer Part Number
AD9516-3
Description
14-Output Clock Generator
Manufacturer
Analog Devices
Datasheet
1.AD9516-3.pdf
(84 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AD9516-3
Manufacturer:
TI
Quantity:
5 510
Company:
Part Number:
AD9516-3BCPZ
Manufacturer:
AD
Quantity:
148
Company:
Part Number:
AD9516-3BCPZ
Manufacturer:
ADI
Quantity:
648
Part Number:
AD9516-3BCPZ
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Reg.
Addr
(Hex) Bit(s) Name
190
190
191
191
191
191
191
Reg.
Addr
(Hex) Bit(s) Name
142
143
143
143
143
143
AD9516-3
Table 57. LVPECL Channel Dividers
<7:4> Divider 0 Low Cycles
<3:0> Divider 0 High Cycles
<7>
<6>
<5>
<4>
<3:0> Divider 0 Phase Offset
<0>
<7:5> OUT9 Output Polarity
<4>
<3>
<2:1> OUT9 LVDS Output Current
<0>
OUT8 Power-Down
OUT9 CMOS B
OUT9 Select LVDS/CMOS
OUT9 Power-Down
Divider 0 Bypass
Divider 0 Nosync
Divider 0 Force High
Divider 0 Start High
Description
Number of clock cycles of the divider input during which divider output stays low.
Number of clock cycles of the divider input during which divider output stays high.
Bypass and power-down the divider; route input to divider output.
<7> = 0; use divider.
<7> = 1; bypass divider.
Nosync.
<6> = 0; obey chip-level SYNC signal.
<6> = 1; ignore chip-level SYNC signal.
Force divider output to high. This requires that nosync also be set.
<5> = 0; divider output forced to low.
<5> = 1; divider output forced to high.
Selects clock output to start high or start low.
<4> = 0; start low.
<4> = 1; start high.
Phase offset.
Description
Power-down output (LVDS/CMOS).
<0> = 0; power on.
<0> = 1; power off.
In CMOS mode, <7:5> select the output polarity of each CMOS output.
In LVDS mode, only <5> determines LVDS polarity.
<7> <6>
0
0
1
1
0
0
1
1
In CMOS mode, turn on/off the CMOS B output. There is no effect in LVDS mode.
<4> = 0; turn off the CMOS B output.
<4> = 1; turn on the CMOS B output.
Select LVDS or CMOS logic levels.
<3> = 0; LVDS.
<3> = 1; CMOS.
Set output current level in LVDS mode. This has no effect in CMOS mode.
<2> <1> Current (mA)
0
0
1
1
Power-down output (LVDS/CMOS).
<0> = 0; power on.
<0> = 1; power off.
0
1
0
1
0
1
0
1
0
1
0
1
1.75
3.5
5.25
7
<5>
0
0
0
0
1
1
1
1
Rev. 0 | Page 74 of 84
OUT9A (CMOS)
Noninverting
Noninverting
Inverting
Inverting
Inverting
Inverting
Noninverting
Noninverting
Recommended Termination (Ω)
100
100
50
50
OUT9B (CMOS)
Inverting
Noninverting
Inverting
Noninverting
Noninverting
Inverting
Noninverting
Inverting
OUT9 (LVDS)
Noninverting
Noninverting
Noninverting
Noninverting
Inverting
Inverting
Inverting
Inverting